Jpn. J. Appl. Phys. 39 (2000) pp. 2321-2324 |Next Article| |Table of Contents|
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Short Note
Analytical Single-Electron Transistor (SET) Model for Design and Analysis of Realistic SET Circuits
Ken Uchida,
Kazuya Matsuzawa,
Junji Koga,
Ryuji Ohba,
Shin-ichi Takagi and
Akira Toriumi
Advanced LSI Technology Laboratory, Toshiba
Corporation, 8 Shinsugita-cho, Isogo-ku, Yokohama 235-8522,
Japan
(Received October 29, 1999; accepted for publication January 13, 2000)
In this work, we propose a compact, physically based, analytical
single-electron transistor (SET) model suitable for the design and
analysis of realistic SET circuits. The model is derived on the
basis of the “orthodox” theory of correlated single-electron
tunneling and the steady-state master equation method. The SET
inverter characteristics are successfully calculated using the model
implemented in the simulation program with integrated circuit
emphasis (SPICE). The hybrid circuit of SETs with
metal-oxide-semiconductor field-effect transistors (MOSFETs) is also
successfully simulated. By utilizing the model, it is clarified
that the drain-voltage-induced shift of the gate voltage dependence
of SET current reaches one-half of the drain voltage in the case of
a completely symmetric SET.
URL:
http://jjap.jsap.jp/link?JJAP/39/2321/
DOI: 10.1143/JJAP.39.2321
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