Jpn. J. Appl. Phys. 43 (2004) pp. 192-196  |Previous Article| |Next Article|  |Table of Contents|
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A Novel Negative Voltage Generator Circuit: Application of a Ferroelectric Capacitor to Low-Power LSIs

Kenji Toyoda, Michihito Ueda, Takashi Ohtsuka, Kiyoshi Morimoto and Kiyoyuki Morita

(Received May 30, 2003; accepted September 19, 2003; published January 13, 2004)

In this paper, a novel voltage generator circuit using a ferroelectric capacitor is described. This circuit consists of two metal-oxide-semiconductor (MOS) transistors, a ferroelectric capacitor and a dielectric capacitor, which can convert a positive input voltage into a negative output voltage. We describe in detail the design and operation principles of the circuit. We have demonstrated the expected circuit operation and evaluated its performance characteristics such as voltage efficiency and verified, using an experimental circuit, that a negative voltage is continuously generated. The magnitude of the measured output voltage value was smaller than that of the simulation result, possibly due to the existence of parasitic resistance in the experimental circuit. The simulation results suggest that our circuit is suitable for reducing the standby leakage current of MOS transistors, one of the most serious power consumption-related problems in advanced CMOS LSIs.

URL: http://jjap.jsap.jp/link?JJAP/43/192/
DOI: 10.1143/JJAP.43.192

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