Jpn. J. Appl. Phys. 43 (2004) pp. 3668-3671 |Previous Article| |Next Article| |Table of Contents|
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Fabrication of 65-nm Holes for 157-nm Lithography
Semiconductor Leading Edge Technologies, Inc. (Selete), 16-1 Onogawa, Tsukuba-shi, Ibaraki 305-8569, Japan
(Received October 29, 2003; revised January 19, 2004; accepted January 27, 2004; published June 29, 2004)
We investigated the use of hole shrink processes along with a bilayer process as a fine-hole-pattern replication technique for 157-nm lithography. A siloxane-type resist and an organic underlayer were used in the bilayer process. The lithographic resolution limit was 90 nm in diameter with a 0.85-numerical-aperture 157-nm microstepper using an attenuated phase-shift mask. Using the bilayer process, we successfully transferred 85-nm-diameter hole patterns in the resist into a 400-nm-thick tetraethylorthosilicate (TEOS) layer. A thermal flow process and the Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) process were used as the hole shrink processes to enhance the resolution. The 120-nm-diameter hole patterns in the resist were shrunk to 80 nm by the thermal flow process and to 65 nm by the RELACS process. In the RELACS process, the diameters of the shrunk hole were less dependent on the hole pitch than in the thermal flow process.
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