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Letter
Simultaneous-Sweep Method for Evaluation of Single-Electron Transistors with Barriers Induced by Gate Electric Field
Hiroshi Inokawa and
Yasuo Takahashi
NTT Basic Research Laboratories, NTT Corporation, 3-1 Morinosato Wakamiya, Atsugi-shi, Kanagawa, 243-0198, Japan
(Received March 18, 2004; accepted June 16, 2004; published July 23, 2004)
In single-electron devices (SEDs) with gate-induced barriers, the barrier height may often be affected by the separate input gate used for controlling the potential of the Coulomb island. To compensate for this adverse effect, we introduce a simultaneous-sweep method, in which the gate voltage for the barrier is changed in inverse relation to the input gate voltage. By using this method, a two-gate narrow-channel metal-oxide-semiconductor (MOS) field-effect transistor was successfully operated as a single-electron transistor (SET). This is the first clear demonstration of a SET with gate-induced barriers in a silicon MOS system, where the presence of a disordered quantum wire or impurity quantum dots is excluded by the independent characterization of the channel using one gate at a time.
URL:
http://jjap.jsap.jp/link?JJAP/43/L1048/
DOI: 10.1143/JJAP.43.L1048
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