Jpn. J. Appl. Phys. 44 (2005) pp. 2210-2213  |Previous Article| |Next Article|  |Table of Contents|
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High-Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics

Kensuke Takahashi, Kenzo Manabe, Ayuka Morioka, Taeko Ikarashi, Takuya Yoshihara, Heiji Watanabe and Toru Tatsumi

(Received October 1, 2004; accepted November 26, 2004; published April 21, 2005)

Dual metal gate transistors with high-k gate dielectrics have been investigated for low-power metal oxide semiconductor (MOS) devices in 45 nm nodes and beyond. Using high-quality HfSiO gate dielectrics, using TiN and Ta for the gate electrode, and minimizing process damage, we have succeeded in markedly improving device performance. Effective work functions of 4.9 eV for TiN and 4.3 eV for Ta on HfSiO were obtained for the first time. Symmetrical threshold voltages of ±0.5 V were realized for these work functions. Small hysteresis and low interface trap densities for both TiN and Ta were obtained, which are almost the same as those of poly-Si/HfSiON transistors. No degradation in electron mobility was achieved for the first time for Ta-NMOS transistors at an effective field of 1.0 MV/cm. The gate leakage current at an equivalent electrical oxide thickness in an inversion of 1.7 nm was suppressed to 1 mA/cm^-2 at a gate bias of Vth+0.6 V.

URL: http://jjap.jsap.jp/link?JJAP/44/2210/
DOI: 10.1143/JJAP.44.2210

References | Citing Articles (5)

1. International Technology Roadmap for Semiconductors 2003 ed.
2. C. Hobbs et al.: Symp. VLSI Tech. (2003) p. 9.
3. W. Tsai, L.-A. Ragnarsson, L. Pantisano, P. J. Chen, B. Onsia, T. Schram, E. Cartier, A. Kerber, E. Young, M. Caymax, S. D. Gendt and M. Heyn: IEDM Tech. Dig. (2003) p. 311.
4. V. Narayanan et al.: Symp. VLSI Tech. (2004) p. 192.
5. S. B. Samavedam et al.: IEDM Tech. Dig. (2002) p. 433.
6. J. Lee, Y.-S. Suh, H. Lazer, R. Jha, J. Gurganus, Y. Lin and V. Misra: IEDM Tech. Dig. (2003) p. 323.
7. D.-G. Park et al.: Symp. VLSI Tech. (2004) p. 186.
8. J. K. Schaeffer et al.: J. Vac. Sci. & Technol. B 21 (2003) 11[AIP Scitation].
9. J. Kedzierski, D. Boyd, P. Ronsheim, S. Zafar, J. Newbury, J. Ott. C. Cabral, Jr., M. Ieong and W. Haensch: IEDM Tech. Dig. (2003) p. 315.
10. E. Cartier et al.: Symp. VLSI Tech. (2004) p. 44.
11. A. Morioka, H. Watanabe, M. Miyamura, T. Tatumi, M. Saitoh, T. Ogura, T. Iwamoto, T. Ikarashi, Y. Saito, Y. Okada, H. Watanabe, Y. Mochiduki and T. Mogami: Symp. VLSI Tech. (2003) p. 165.
12. J. Lee, H. Zhong, Y.-S. Suh, G. Heuss, J. Gurganus, B. Chen and V. Misra: IEDM Tech. Dig. (2002) p. 359.
13. B. Maiti, P. J. Tobin, C. Hobbs, R. I. Hegde, F. Huang, D. L. O'Meara, D. Jovanovic, M. Mendicino, J. Chen, D. Connelly, O. Adetutu, J. Mogab, J. Candelaria and L. B. La: IEDM Tech. Dig. (1998) p. 781.
14. T. Iwamoto et al.: IEDM Tech. Dig. (2003) p. 639.
15. K. Manabe, K. Takahashi, T. Ikarashi, A. Morioka, H. Watanabe, T. Yoshihara and T. Tatsumi: Ext. Abst. Int. Conf. Solid State Devices and Materials (2004) p. 18.