Jpn. J. Appl. Phys. 46 (2007) pp. 2231-2237 |Previous Article| |Next Article| |Table of Contents|
|Full Text PDF (310K)| |Buy This Article|
Mixed Digital–Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search
Research Center for Nanodevices and Systems, Hiroshima University, 1-4-2 Kagamiyama, Higashi-Hiroshima, Hiroshima 739-8527, Japan
(Received September 11, 2006; accepted January 12, 2007; published online April 24, 2007)
In this paper, an associative memory architecture with mixed digital–analog search circuitry is proposed, which enables a fully-parallel nearest match-data search based on the Euclidean distance between input pattern and stored reference patterns. A test chip, implementing the proposed architecture, was designed in 0.35 µm complementary metal–oxide–semiconductor (CMOS) technology with two-poly and three-metal layers. The nearest-match unit consumes only 0.64 mm2 (12.5% of the total design area), while the whole chip area is 5.12 mm2. The layout-based simulated winner-search time, the time to determine the best-matching reference-data word for an input-data word among a database of 64 reference patterns (5-bit, 16 units), is lower than 160 ns. This corresponds to a performance requirement of 27 giga operations per second (GOPS)/mm2, if a general purpose computer with the same chip area would have to run the same workload. Furthermore, the power dissipation of the designed test chip is only about 38 mW/mm2 at this high processing performance.
- H. J. Mattausch, T. Gyohten, Y. Soda, and T. Koide: IEEE J. Solid-State Circuits 37 (2002) 218.
- Y. Yano, T. Koide, and H. J. Mattausch: Ext. Abstr. Solid State Devices and Materials, 2002, p. 254.
- Y. Oike, M. Ikeda, and K. Asada: Proc. IP Based System-on-Chip Design Forum & Exhib., 2004, p. 127.
- Y. Oike, M. Ikeda, and K. Asada: Proc. IEEE Custom Integrated Circuits Conf., 2004, p. 295.
- M. Miyazawa, P. Zeng, N. Iso, and T. Hirata: IEEE Trans. Pattern Anal. Mach. Intell. 28 (2006) 1127.
- Y. Tulay and J. S. Marsland: IEEE Conf. Neural Networks, 1996, p. 974.
- O. Landolt, E. Vittoz, and P. Heim:
Electron. Lett. 28 (1992) 352[AIP Scitation].
- P. Hasler, B. A. Minch, J. Dugger, and C. Dorio: in Learning on Silicon: Adaptive VLSI Neural Systems, ed. G. Cauwenberghs and M. A. Bayoumi (Kluwer, Boston, 1999) p. 33.
- M. Freeman, M. Weeks, and J. Austin: IADIS Int. Conf. Applied Computing, 2005, p. 329.
- K. Tsang and B. W. Y. Wei: IEEE Trans. VLSI Syst. 2 (1994) 360.
- S. Churcher, A. F. Murray, and H. M. Reekie:
Electron. Lett. 29 (1993) 1603[AIP Scitation].
- K. Bult and H. Wallinga: IEEE J. Solid-State Circuits 22 (1987) 357.
- S. M. Saif, H. M. Abbas, and S. M. Nassar: Int. Joint Conf. Neural Networks, 2006, p. 2815.