(Received July 11, 2007; revised November 13, 2007; accepted November 16, 2007; published online March 21, 2008)
The concept of a counting-based digital-to-analog converter (CNT-DAC) is proposed to realize a compact column driver circuit for system-on-panel (SoP) applications. The traditional ramp DAC is very promising in the circuit-area respect, because it replaces the area-consuming read only memory (ROM)-type decoder with a counter; however, it is not widely used for display column drivers because it has several problems such as ramp signal distortion, charge sharing between column lines and pixel electrode and ramp signal generation. The CNT-DAC was inspired by the ramp DAC, which uses a counter instead of an area-consuming ROM-type decoder but can avoid the problems mentioned above by using a resistor string at each channel and a global shift register. Instead of designing an 8-bit DAC with the counting-based DAC alone, we combine the 3-bit traditional decoder-based DAC and the 5-bit CNT-DAC, because the 8-bit CNT-DAC needs a clock frequency of about 20 MHz for a portrait qVGA format (H: 240, V: 320), which is a fairy difficult requirement to meet. For a 2-in. diagonal portrait qVGA AMOLED panel, the circuit area of one channel DAC is 73×1,010 µm2 with the design rule of 2 µm and a TFT channel length of 4 µm. The total power consumption of the CNT-DAC is about 3.2 mW; the static power consumption due to the resistor string at each channel is 1.7 mW, the dynamic power consumption for driving the column lines is about 1.0 mW, and the global shift register consumes about 0.5 mW.