Jpn. J. Appl. Phys. 48 (2009) 021203 (3 pages) |Previous Article| |Next Article| |Table of Contents|
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Performance Improvement of Polycrystalline Silicon Nanowire Thin-Film Transistors by a High-k Capping Layer
Ko-Hui Lee1,
Hsing-Hui Hsu1,
Horng-Chih Lin1,2, and
Tiao-Yuan Huang1
1Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan 300, R.O.C.
2National Nano Device Labs., 26 Prosperity Road I, Science-based Industrial Park, Hsinchu, Taiwan 300, R.O.C.
(Received July 15, 2008; accepted November 1, 2008; published online February 20, 2009)
In this work, a novel polycrystalline silicon (poly-Si) nanowire thin-film transistor (NW-TFT) with side-gated configuration and a high-k material capping was fabricated and characterized. It was found that the gate fringing field effect via the high-k passivation layer can effectively improve the device performance in terms of higher ON current, larger ON/OFF current ratio, and steeper subthreshold slope (SS). The drain-induced barrier lowering (DIBL) effect is also effectively suppressed owing to better gate control.
URL:
http://jjap.jsap.jp/link?JJAP/48/021203/
DOI: 10.1143/JJAP.48.021203
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