Jpn. J. Appl. Phys. 48 (2009) 06FD09 (5 pages)  |Previous Article| |Next Article|  |Table of Contents|
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Effects of Geometrical Fin Parameters on Transfer Characteristics in Triple-Gate Fin Field Effect Transistors

Jae-Joon Song, Dae-hyun Moon, and Ohyun Kim

(Received November 27, 2008; accepted January 20, 2009; published online June 22, 2009)

We examined the effects of device parameters on the transfer characteristics of triple-gate fin field-effect transistors (FinFETs) using three-dimensional device simulations. Channels were observed to form separately in the corner and main regions of triple-gate FinFETs with a heavy channel doping (for threshold voltage control using a polycrystalline silicon gate). The threshold voltages of the corner and main regions were determined using the transconductance change method. The phenomenon of channel separation is present only if high doping concentrations and corners with no radius of curvature are used in long-channel devices. For channel doping concentrations higher than 5 ×10¹⁸ cm^-3, the corner transistor turns on earlier than the main transistor. This effect is significantly reduced by the use of rounded corners, thin gate oxides, and high dielectrics. However, the earlier conduction of corner regions is not effectively suppressed in body-tied FinFETs even though the corner regions are rounded with a large radius of curvature.

URL: http://jjap.jsap.jp/link?JJAP/48/06FD09/
DOI: 10.1143/JJAP.48.06FD09

References

1. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, and W. Haensch: IEDM Tech. Dig., 2002, p. 247.
2. F.-L. Yang, H.-Y. Chen, F.-C. Chen, C.-C. Huang, C.-Y. Chang, H.-K. Chiu, C-.C. Lee, C.-C. Chen, H.-T. Huang, C.-J. Chen, H.-J. Tao, Y.-C. Yeo, M.-S. Liang, and C. Hu: IEDM Tech. Dig., 2002, p. 255.
3. T. Park, H. J. Cho, J. D. Choe, S. Y. Han, S.-M. Jung, J. H. Jeong, B. Y. Nam, O. I. Kwon, J. N. Han, H. S. Kang, M. C. Chae, G. S. Yeo, S. W. Lee, D. Y. Lee, D. Park, K. Kim, E. Yoon, and J. H. Lee: IEDM Tech. Dig., 2003, p. 27.
4. T. Park, S. Choi, D. H. Lee, J. R. Yoo, B. C. Lee, J. Y. Kim, C. G. Lee, K. K. Chi, S. H. Hong, S. J. Hyun, Y. G. Shin, J. N. Han, I. S. Park, U. I. Chung, J. T. Moon, E. Yoon, and J. H. Lee: Symp. VLSI Technology Dig. Tech., 2003, p. 135.
5. T. Park, D. Park, J. H. Chung, E. J. Yoon, S. M. Kim, H. J. Cho, J. D. Choe, J. H. Choi, B. M. Yoon, J. J. Han, B. H. Kim, E. Yoon, and J. H. Lee: Tech. Dig. IEEE Device Research Conf., 2003, p. 33.
6. J.-H. Lee, T. Park, E. Yoon, and Y. J. Park: Proc. Silicon Nanoelectronics Workshop, 2003, p. 102.
7. K.-R. Han, B.-K. Choi, T. Park, E. Yoon, I.-Y. Chung, and J.-H. Lee: Jpn. J. Appl. Phys. 44 (2005) 2176[JSAP].
8. K.-R. Han, B.-K. Choi, H.-I. Kwon, and J.-H. Lee: Jpn. J. Appl. Phys. 47 (2008) 4385[JSAP].
9. A. Burenkov and J. Lorenz: Proc. European Solid-State Device Research Conf., 2003, p. 135.
10. J. G. Fossum, J.-W. Yang, and V. P. Trivedi: IEEE Electron Device Lett. 24 (2003) 745[CrossRef].
11. M. Stadele, R. J. Luyken, M. Rooze, M. Specht, W. Rosner, L. Dreeskornfeld, J. Hartwich, F. Hofmann, J. Kretz, E. Landgraf, and L. Risch: Proc. European Solid-State Device Research Conf., 2004, p. 165.
12. SILVACO International, ATLAS User's Manual–Device Simulation Software, 2007, Version 5.12.1.R.
13. X. Wu, P. C. H. Chan, and M. Chan: IEEE Trans. Electron Devices 52 (2005) 63[CrossRef].
14. H.-S. Wong, M. H. White, T. J. Krutsick, and R. V. Booth: Solid-State Electron. 30 (1987) 953[CrossRef].
15. P. Francis, A. Terao, D. Flandre, and F. Van de Wiele: Solid-State Electron. 38 (1995) 171[CrossRef].
16. J. P. Colinge, J. W. Park, and W. Xiong: IEEE Electron Device Lett. 24 (2003) 515[CrossRef].