Jpn. J. Appl. Phys. 49 (2010) 04DB04 (5 pages)  |Previous Article| |Next Article|  |Table of Contents|
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Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-k/Cu Interconnects

Ippei Kume, Naoya Inoue, Shinobu Saito, Naoya Furutake, Jun Kawahara, and Yoshihiro Hayashi

(Received October 11, 2009; revised December 21, 2009; accepted December 24, 2009; published online April 20, 2010)

A highly reliable Cu dual-damascene interconnect (DDI) was developed in a molecular-pore-stack (MPS) SiOCH film (k = 2.5) with precise taper angle control at the top and bottom of via holes. The durable MPS film with the carbon-rich composition revealed no reliability deterioration in the time-dependent dielectric breakdown (TDDB) between the 140-nm pitched lines. The stres-induced voiding (SiV) was suppressed completely by precise taper angle control both at the top and bottom of via holes. A shallow-tapered via and a stepped via, in which these top taper angles (θ_top) were greater than 45° while keeping the bottom angle (θ_btm) steep at approximately 90°, improved the SiV reliability referred to a deep-tapered via with θ_btm≪90°. Finite element method (FEM) simulation well explains the dependence of SiV reliability on both θ_top and θ_btm; the increment of θ_top reduces the stress gradient under the via, while the decrease in θ_btm enlarges the stress gradient. Namely, the precise taper angle control of both the top and bottom via is very important to improve the SiV reliability, and the shallow-tapered and the stepped vias in the MPS film were confirmed to achieve high endurance against the SiV due to relaxation of the stress gradient under the via.

URL: http://jjap.jsap.jp/link?JJAP/49/04DB04/
DOI: 10.1143/JJAP.49.04DB04

References | Citing Articles (3)

1. M. Ueki, M. Tagami, F. Ito, I. Kume, H. Yamamoto, J. Kawahara, N. Inoue, K. Hijioka, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, N. Okada, and Y. Hayashi: IEDM Tech. Dig., 2008, p. 619.
2. D. Ingerly, S. Agraharam, D. Becher, V. Chikarmane, K. Fischer, R. Grover, M. Goodner, S. Haight, J. He, T. Ibrahim, S. Joshi, H. Kothari, K. Lee, Y. Lin, C. Litteken, H. Liu, E. Mays, P. Moon, T. Mule, S. Nolen, N. Patel, S. Pradhan, J. Robinson, P. Ramanarayanan, S. Sattiraju, T. Schroeder, S. Williams, and P. Yashar: Proc. Int. Interconnect Technology Conf., 2008, p. 216.
3. V. Arnal, A. Farcy, M. Aimadeddine, B. Icard, C. Guedj, S. Maitrejean, J. Todeschini, W. Besling, P. Brun, E. Ollier, J. P. Jacquemin, R. Delsol, P. Vannier, M. Mellier, E. Richard, R. Fox, G. Imbert, Y. Lefriec, A. Toffoli, and J. Torres: Proc. Int. Interconnect Technology Conf., 2006, p. 213.
4. M. Ueki, T. Onodera, A. Ishikawa, S. Hoshino, and Y. Hayashi: Jpn. J. Appl. Phys. 48 (2009) 04C029[JSAP].
5. N. Inoue, N. Furutake, F. Ito, H. Yamamoto, T. Takeuchi, and Y. Hayashi: Jpn. J. Appl. Phys. 47 (2008) 2468[JSAP].
6. Y. Hayashi, H. Ohtake, J. Kawahara, M. Tada, S. Saito, N. Inoue, F. Ito, M. Tagami, M. Ueki, N. Furutake, T. Takeuchi, H. Yamamoto, and M. Abe: IEEE Trans. Semicond. Manuf. 21 (2008) 469.
7. M. Morgan, E. T. Ryan, J. H. Zhao, C. Hu, T. Cho, and P. S. Ho: Annu. Rev. Mater. Sci. 30 (2000) 645.
8. K. Maex, M. R. Baklanov, D. Shamiryan, F. Lacopi, S. H. Brongersma, and Z. S. Yanovitskaya: J. Appl. Phys. 93 (2003) 8793[AIP Scitation].
9. L. Broussous, W. Puyrenier, D. Rebiscoulb, V. Rouessac, and A. Ayral: Proc. Int. Interconnect Technology Conf., 2008, p. 300.
10. H. Shi, J. Bao, H. Huang, B. Chao, S. Smith, Y. Sun, and P. S. Ho: Proc. Int. Interconnect Technology Conf., 2008, p. 31.
11. W. H. Tseng, C. Yang, W. J. Wu, J. C. Hsiung, Y. L. Lin, T. I. Bao, J. L. Yang, J. H. Shieh, C. C. Jeng, J. C. Lin, J. L. Huang, H. C. Chen, H. Lo, J. Wang, C. H. Yu, and M. S. Lang: Proc. Int. Interconnect Technology Conf., 2005, p. 165.
12. H. Ohtake, S. Saito, M. Tagami, M. Tada, M. Abe, N. Furutake, and Y. Hayashi: Ext. Abstr. Solid State Devices and Materials, 2005, p. 300.
13. H. Tsuchikawa, Y. Mizushima, T. Nakamura, T. Suzuki, and H. Nakajima: Jpn. J. Appl. Phys. 45 (2006) 714[JSAP].
14. M. Abe, N. Furutake, S. Saito, N. Inoue, and Y. Hayashi: Jpn. J. Appl. Phys. 44 (2005) 2294[JSAP].
15. T. Nakamura and T. Suzuki: Proc. Solid State Devices and Materials, 2007, p. 914.
16. Rika Nenpyo, ed. National Astronomincal Observatory (Maruzen, Tokyo, 2004) [in Japanese].
17. D. Gan, G. Wang, and P. S. Ho: Proc. Int. Interconnect Technology Conf., 2002, p. 271.