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Jpn. J. Appl. Phys. 51 (2012) 02BC06 (5 pages)  |Previous Article| |Next Article|  |Table of Contents|
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Suppression of Within-Device Variability in Intrinsic Channel Tri-Gate Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors

Ke Mao, Tomoko Mizutani, Anil Kumar, Takuya Saraya, and Toshiro Hiramoto

Institute of Industrial Science, University of Tokyo, Meguro, Tokyo 153-8505, Japan

(Received September 26, 2011; revised October 28, 2011; accepted November 10, 2011; published online February 20, 2012)

In this paper, the variabilities of threshold voltage (VTH), drain-induced barrier lowering (DIBL), and current onset voltage (COV) in intrinsic channel silicon nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) were evaluated and compared with those of conventional bulk and fully depleted (FD) silicon-on-insulator (SOI) MOSFETs. The random component of variability is extracted by a “within-device” variability method to exclude the systematic component. It is found that the within-device variabilities of DIBL and COV as well as VTH are extremely small in intrinsic channel nanowire MOSFETs owing to the non-intentionally doped channel and small gate workfunction variability. The intrinsic channel nanowire MOSFET is promising for a future scaled device structure in terms of not only the short channel effect suppression but also the variability suppression.

URL: http://jjap.jsap.jp/link?JJAP/51/02BC06/
DOI: 10.1143/JJAP.51.02BC06


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References

  1. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers: IEEE J. Solid-State Circuits 24 (1989) 1433.
  2. K. J. Kuhn: IEDM Tech. Dig., 2007, p. 467.
  3. T. Mizuno, J. Okamura, and A. Toriumi: IEEE Trans. Electron Devices 41 (1994) 2216[CrossRef].
  4. A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva: IEEE Trans. Electron Devices 50 (2003) 1837[CrossRef].
  5. A. Asenov: VLSI Tech. Dig., 2007, p. 86.
  6. F. Tachibana and T. Hiramoto: Jpn. J. Appl. Phys. 44 (2005) 2147[JSAP].
  7. A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto: Appl. Phys. Express 2 (2009) 024501[JSAP].
  8. A. T. Putra, A. Nishida, S. Kamohara, T. Tsunomura, and T. Hiramoto: Jpn. J. Appl. Phys. 48 (2009) 044502[JSAP].
  9. A. T. Putra, T. Tsunomura, A. Nishida, S. Kamohara, K. Takeuchi, and T. Hiramoto: Jpn. J. Appl. Phys. 48 (2009) 044502[JSAP].
  10. T. Tsunomura, A. Nishida, and T. Hiramoto: Jpn. J. Appl. Phys. 48 (2009) 124505[JSAP].
  11. T. Tsunomura, A. Nishida, and T. Hiramoto: Jpn. J. Appl. Phys. 49 (2010) 054101[JSAP].
  12. S. Ohkawa, M. Aoki, and H. Masuda: IEEE Trans. Semicond. Manuf. 17 (2004) 155.
  13. M. Aoki, S. Ohkawa, and H. Masuda: Proc. 17th IEEE ICMTS, 2004, p. 201.
  14. M. E. Mason: Symp. VLSI Technology Dig., 2007, p. 90.
  15. H. Onodera: Symp. VLSI Technology Dig., 2007, p. 92.
  16. Y. Yasuda, M. Takamiya, and T. Hiramoto: IEEE Trans. Electron Devices 47 (2000) 1838[CrossRef].
  17. K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto: IEDM Tech. Dig., 2007, p. 467.
  18. T. Tsunomura, A. Nishida, and T. Hiramoto: IEEE Trans. Electron Devices 56 (2009) 2073[CrossRef].
  19. T. Tsunomura, F. Yano, A. Nishida, and T. Hiramoto: Jpn. J. Appl. Phys. 49 (2010) 074104[JSAP].
  20. T. Tsunomura, A. Nishida, and T. Hiramoto: IEEE Trans. Electron Devices 58 (2011) 364[CrossRef].
  21. M. Miyamura, T. Nagumo, K. Takeuchi, K. Takeda, and M. Hane: IEDM Tech. Dig., 2008, p. 447.
  22. T. Tsunomura, A. Kumar, T. Mizutani, C. Lee, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami: Symp. VLSI Technology Dig., 2010, p. 97.
  23. T. Tsunomura, A. Kumar, T. Mizutani, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami: Appl. Phys. Express 3 (2010) 114201[JSAP].
  24. T. Tsunomura, A. Kumar, T. Mizutani, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto, and T. Mogami: Jpn. J. Appl. Phys. 50 (2011) 04DC08[JSAP].
  25. A. Kumar, T. Mizutani, K. Shimizu, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, and T. Hiramoto: Silicon Nanoelectronics Workshop Abstr., 2010, p. 7.
  26. T. Mizutani, A. Kumar, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, and T. Hiramoto: Silicon Nanoelectronics Workshop Abstr., 2010, p. 81.
  27. X. Song, M. Suzuki, T. Saraya, A. Nishida, T. Tsunomura, S. Kamohara, K. Takeuchi, S. Inaba, T. Mogami, and T. Hiramoto: IEDM Tech. Dig., 2010, p. 62.
  28. T. Hiramoto, T. Mizutani, A. Kumar, A. Nishida, T. Tsunomura, S. Inaba, K. Takeuchi, S. Kamohara, and T. Mogam: IEEE SOI Conf., 2010, p. 170.
  29. K. Zaitsu, M. Saitoh, Y. Nakabayashi, T. Ishihara, and T. Numata: Jpn. J. Appl. Phys. 50 (2011) 04DC10[JSAP].
  30. O. Faynot, F. Andrieu, O. Weber, C. Fenouillet-Béranger, P. Perreau, J. Mazurier, T. Benoist, O. Rozeau, T. Poiroux, M. Vinet, L. Grenouillet, J.-P. Noel, N. Posseme, S. Barnola, F. Martin, C. Lapeyre, M. Cassé, X. Garros, M.-A. Jaud, O. Thomas, G. Cibrario, L. Tosti, L. Brévard, C. Tabone, P. Gaud, S. Barraud, T. Ernst, and S. Deleonibus: IEDM Tech. Dig., 2010, p. 50.
  31. T. Tanaka, T. Usuki, Y. Momiyama, and T. Sugii: VLSI Technology Dig., 2000, p. 136.
  32. M. Saitoh, K. Ota, C. Tanaka, Y. Nakabayashi, K. Uchida, and T. Numata: VLSI Technology Dig., 2011, p. 132.
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