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Jpn. J. Appl. Phys. 51 (2012) 04DC06 (5 pages)  |Previous Article| |Next Article|  |Table of Contents|
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Advantages of Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors over Planar Ones in Noise Properties

Wei Feng1,2, Ranga Hettiarachchi1,2, Soshi Sato3, Kuniyuki Kakushima4, Masaaki Niwa1,2, Hiroshi Iwai3, Keisaku Yamada1,2, and Kenji Ohmori1,2

1Graduate School of Pure and Applied Sciences, University of Tsukuba, Tsukuba, Ibaraki 305-8573, Japan
2Core Research for Evolutional Science and Technology, Japan Science and Technology Agency (JST-CREST), Chiyoda, Tokyo 102-0075, Japan
3Frontier Research Center, Tokyo Institute of Technology, Yokohama 226-8502, Japan
4Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama 226-8502, Japan

(Received September 26, 2011; accepted December 15, 2011; published online April 20, 2012)

We have investigated the low-frequency noise behavior of silicon nanowire metal–oxide–semiconductor field-effect transistors (NWFETs) by comparison with that of a planar FET. We have found that the NWFET exhibits lower noise intensity than the planar FET. By analyzing the factors influential to noise intensity, one of the most possible origins of this advantage of the NWFET results from the electron distribution in the channel in NWFET. Owing to quantum confinement, the position of charge-centroids in the channel of NWFET is located further from the interface, resulting in the lower trapping probability between the electrons and oxide traps. These results clearly demonstrate the advantage of three-dimensional structures in static and noise properties.

URL: http://jjap.jsap.jp/link?JJAP/51/04DC06/
DOI: 10.1143/JJAP.51.04DC06


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