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64 kbit Ferroelectric-Gate-Transistor-Integrated NAND Flash Memory with 7.5 V Program and Long Data Retention

Xizhen Zhang, Mitsue Takahashi, Ken Takeuchi¹, and Shigeki Sakai

(Received September 26, 2011; accepted December 6, 2011; published online April 20, 2012)

A 64 kbit (kb) one-transistor-type ferroelectric memory array was fabricated and characterized. Pt/SrBi₂Ta₂O₉/Hf–Al–O/Si ferroelectric-gate field-effect transistors (FeFETs) were used as the memory cells. The gate length and width were 5 and 5 µm, respectively. The array design was based on NAND flash memory organized as 8 word lines × 32 blocks × 256 bit lines. Erase, program, and nondestructive-read operations were demonstrated in every block. Threshold-voltage (V_th) reading of all the 64 kb memory cells showed a clear separation between their all-erased and all-programmed states. A checkerboard pattern was also programmed in a block and the two distinguishable V_th distributions were read out. The V_th retention of a block of 2 kb memory cells showed no significant degradation after two days.

URL: http://jjap.jsap.jp/link?JJAP/51/04DD01/
DOI: 10.1143/JJAP.51.04DD01

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