Jpn. J. Appl. Phys. 51 (2012) 04DD02 (7 pages)  |Previous Article| |Next Article|  |Table of Contents|
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Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell

Kousuke Miyaji, Yasuhiro Shinozuka, and Ken Takeuchi

(Received September 26, 2011; accepted January 4, 2012; published online April 20, 2012)

This paper proposes for the first time the completely complemental metal–oxide–semiconductor (CMOS) compatible embedded flash memory with the small cell size as well as the lowest process cost. The single transistor cell with the minimum channel length and width realizes the ideal smallest cell. The non-volatile memory operation is realized with locally injected electrons at the drain-edge by the hot electron injection. This paper also proposes the novel forward-bias assisted erase. The proposed memory is experimentally demonstrated with the 65 nm standard CMOS process without additional process or mask. The cell size is 10F² with the 65 nm CMOS logic design rule. The excellent reliability such as 100-times program/erase endurance, 10-year data retention and high immunity to the read/program/erase disturb is also experimentally demonstrated. The proposed cell is the ideal candidate for the code-storage embedded non-volatile memories in system-on-chip and microcontroller unit.

URL: http://jjap.jsap.jp/link?JJAP/51/04DD02/
DOI: 10.1143/JJAP.51.04DD02

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