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Re-Examination of Performance and Reliability Degradation in Metal–Oxide–Nitride–Oxide–Semiconductor Memory with Ultrathin SiN Charge Trap Layers
Haruka Kusai,
Misako Morota,
Masato Oda,
Shosuke Fujii,
Kiwamu Sakuma, and
Masato Koyama
Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, Yokohama 235-8522, Japan
(Received September 26, 2011; accepted December 12, 2011; published online April 20, 2012)
We demonstrated that the degradation of program characteristics in metal–oxide–nitride–oxide–semiconductor (MONOS) devices consisting of an ultrathin (∼2 nm) SiN charge trap layer is due to a decrease in the electron capture efficiency, instead of a reduction in the number of available trap sites. From the data retention properties with applied gate bias voltage, we clarified that charge loss through the tunnel layer during data retention becomes more significant with decreasing SiN thickness. These results indicate that to improve the performance and reliability of MONOS devices with an ultrathin SiN charge trap layer, measures must be taken to enhance the capture cross section of the traps and to inhibit carrier motion in the SiN layer simultaneously.
URL:
http://jjap.jsap.jp/link?JJAP/51/04DD04/
DOI: 10.1143/JJAP.51.04DD04
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