Jpn. J. Appl. Phys. 51 (2012) 04DE02 (3 pages)  |Previous Article| |Next Article|  |Table of Contents|
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Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing

Takashi Matsumoto¹, Hiroaki Makino¹, Kazutoshi Kobayashi^2,3, and Hidetoshi Onodera^1,3

(Received September 26, 2011; accepted December 12, 2011; published online April 20, 2012)

We propose a multicore large-scale integration (LSI) lifetime extension method, which is based on negative bias temperature instability (NBTI) recovery-based self-healing and circuit parallelization. NBTI recovery is characterized by the recently proposed NBTI sensor with 400 ns measurement delay that measures the off-leak current of p-channel metal–oxide–semiconductor (PMOS) transistors. The circuit is fabricated in a commercial 65 nm complementary MOS (CMOS) technology. It is found that the recoverable component of the LSI performance characterized by the off-leak current remains almost constant after repeatedly adding NBTI stress. The NBTI stress corresponds to circuit operation for several years at room temperature and a nominal operating voltage. It is also found that the amount of NBTI recovery can be tuned by the relaxation time in a real application, and it follows log t from 400 ns to 3000 s. It is shown that for multicore LSI, by recovering one of the n + 1 cores, the n-core LSI system does not stop and the lifetime can be extended by NBTI recovery. For the first time, transforming silicon area into LSI reliability is shown to be a promising and realistic concept for the ever-shrinking CMOS technology.

URL: http://jjap.jsap.jp/link?JJAP/51/04DE02/
DOI: 10.1143/JJAP.51.04DE02

References

1. S. Borkar: IEEE Micro 25 [6] (2005) 10.
2. M. Alam: Microelectron. Reliab. 48 (2008) 1114.
3. H. Onodera: IEDM Tech. Dig., 2008, p. 701.
4. D. K. Schroder and J. A. Babcock: J. Appl. Phys. 94 (2003) 1[AIP Scitation].
5. J. H. Sthathis and S. Zafar: Microelectron. Reliab. 46 (2006) 270.
6. M. Alam: IEDM Tech. Dig., 2003, p. 345.
7. H. Reisinger, O. Blank, W. Heinrigs, A. Muhlhoff, W. Gustin, and C. Schlunder: Proc. IRPS, 2006, p. 448.
8. C. Shen, M. F. Li, C. E. Foo, T. Yang, D. M. Huang, A. Yap, G. S. Samudra, and Y. C. Yeo: IEDM Tech. Dig., 2006, p. 333.
9. Z. Q. Teo, D. S. Ang, and G. A. Du: Proc. IRPS, 2009, p. 1002.
10. T. Grasser, B. Kaczer, W. Goes, T. Aichinger, P. Hehenberger, and M. Nelhiebel: Proc. IRPS, 2009, p. 33.
11. A. E. Islam, S. Mahapatra, S. Deora, V. D. Maheta, and M. A. Alam: IEDM Tech. Dig., 2009, p. 733.
12. H. Reisinger, T. Grasser, W. Gustin, and C. Schlunder: Proc. IRPS, 2010, p. 7.
13. T. Grasser, H. Reisinger, P. J. Wagner, F. Schanovsky, W. Goes, and B. Kaczer: Proc. IRPS, 2010, p. 16.
14. B. Kaczer, T. Grasser, Ph. J. Roussel, J. Franco, R. Degraeve, L. A. Ragnarsson, E. Simoen, G. Groeseneken, and H. Reisinger: Proc. IRPS, 2010, p. 26.
15. V. Huard: Proc. IRPS, 2010, p. 33.
16. T. Matsumoto, H. Makino, K. Kobayashi, and H. Onodera: Jpn. J. Appl. Phys. 50 (2011) 04DE06[JSAP].
17. T. Matsumoto, H. Makino, K. Kobayashi, and H. Onodera: Ext. Abstr. Solid State Devices and Materials, 2011, p. 1045.
18. J. Howard, S. Dighe, Y. Hoskote, S. Vangal, D. Finan, G. Ruhl, D. Jenkins, H. Wilson, N. Borkar, G. Schrom, F. Pailet, S. Jain, T. Jacob, S. Yada, S. Marella, P. Salihundam, V. Erraguntla, M. Konow, M. Riepen, G. Droege, J. Lindemann, M. Gries, T. Apel, K. Henriss, T. Lund-Larsen, S. Steibl, S. Borkar, V. De, R. Van Der Wijingaart, and T. Mattson: ISSCC Tech. Dig., 2010, p. 108.
19. A. Chandrakasan, S. Sheng, and R. Brodersen: IEEE J. Solid-State Circuits 27 (1992) 473.
20. T. Aichinger, M. Nelhiebel, and T. Grasser: Proc. IRPS, 2009, p. 2.