Jpn. J. Appl. Phys. 22 (1983) Supplement 22-1 pp. 121-124  |Previous Article| |Next Article|  |Table of Contents|
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14th Conf. (1982 Int.) Solid State Devices, Tokyo, 1982

A 10 Bit All-Parallel A/D Converter

Michihiro Inoue, Toyoki Takemoto, Hideaki Sadamatsu, Akira Matsuzawa, Kunitoshi Aono and Kazuhiko Tsuji

This paper describes a 10 bit all-parallel analog-to-digital converter with 20 MHz conversion rate.
Static accuracy was achieved by suppressing the offset voltage of pair transistors to be below 0.5 mV, and by laser trimming technology to improve nonlinearity of the dc reference voltages. In regard to dynamic accuracy, an SNR of 53 dB was observed at input signal frequencies up to 1 MHz.
A 3 µm bipolar process is adopted, which integrates nearly 40,000 elements onto a 9.2×9.8 mm chip.

URL: http://jjap.jsap.jp/link?JJAPS/22S1/121/