Jpn. J. Appl. Phys. 22 (1983) Supplement 22-1 pp. 447-450  |Previous Article| |Next Article|  |Table of Contents|
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14th Conf. (1982 Int.) Solid State Devices, Tokyo, 1982

A Josephson Full Adder Circuit Using Four-Junction Logic (4JL) Gates

Hiroshi Nakagawa, Eiichi Sogawa, Susumu Takada and Hisao Hayakawa

A full adder Josephson circuit consisting of direct-coupled four-junction logic gates (4JL gate) has been designed and fabricated by a 5 µm lead-alloy junction technology. Carry signal is generated by the combination of two-input OR- and AND-gates, and sum signal is generated by two exclusive-OR gates connected with a four switching gates chain to obtain a delayed timing signal. The circuit of 21 gates has been found to be quite stable for add opeations at a total power current level of 3.5 mA±0.23 mA with a total power dissipation of 42 µW. By dynamic simulations of the circuit, carry and sum logic times are evaluated to be about 70 ps and 220 ps, respectively.

URL: http://jjap.jsap.jp/link?JJAPS/22S1/447/