Jpn. J. Appl. Phys. 22 (1983) Supplement 22-1 pp. 63-67  |Previous Article| |Next Article|  |Table of Contents|
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14th Conf. (1982 Int.) Solid State Devices, Tokyo, 1982

Redundancy Techniques for Dynamic RAMs

Katsuhiro Shimohigashi¹, Masamichi Ishihara² and Shinji Shimizu²

This paper describes redundancy techniques designed for a 256 K dynamic RAM with polysilicon fuses which are used as electrically programmable ROMs. It shows that four spare rows and columns are suitable for obtaining the maximum yield improvement in the RAM. The first level polysilicon is used for the fuse and a two step etching process is employed to remove the PSG and final passivation layers.
Fusing characteristics have been studied and a model based on a thermal equation is presented.
A 256 K dynamic RAM test device with redundancy was designed and fabricated using 2 µm lithography. It was found that the yield could be improved by a factor of 5–10, if four spare rows and columns were incorporated.

URL: http://jjap.jsap.jp/link?JJAPS/22S1/63/