Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory

2013-04-22T09:00:00+09:00

Authors: Bong-Su Jo, Ho-Jung Kang, Sung-Min Joe, Min-Kyu Jeong, Kyung-Rok Han, Sung-Kye Park, Byung-Gook Park, and Jong-Ho Lee
We characterized normalized noise power density (S_{I}/I_{BL}^{2}) and bit-line (BL) current fluctuation (ΔI_{BL}) using traps generated applying cycling stress in 26 nm NAND flash memory. The ΔI_{BL}, S_{I}/I_{BL}^{2}, and capture (τ_{c}) and emission times (τ_{e}) of random telegraph noise (RTN) were measured before and after cycling stress, respectively. With cycling stress, traps were generated, and S_{I}/I_{BL}^{2} and ΔI_{BL} were increased significantly. The τ_{c} and τ_{e} of RTN after cycling stress are similar with to those before cycling stress. RTN was characterized in terms of the trap position in the three-dimensional space (x_{T}, y_{T}, and z_{T}) of the tunneling oxide and trap energy (E_{T}). three-dimensional technology computer-aided design (TCAD) simulation was used to determine the position of z_{T} through the effect of adjacent BL cells.

Interfacial Reaction Mechanisms in Al_{2}O_{3}/Ge Structure by Oxygen Radical Process

2013-04-22T09:00:00+09:00

Authors: Kimihiko Kato, Shigehisa Shibayama, Mitsuo Sakashita, Wakana Takeuchi, Noriyuki Taoka, Osamu Nakatsuka, and Shigeaki Zaima
We have investigated the impacts of the oxygen radical process on the interfacial structures and electrical properties of Al_{2}O_{3}/Ge structures to clarify the interfacial reaction mechanisms. At a low process temperature, the oxygen radical process can introduce oxygen atoms to the Al_{2}O_{3}/Ge interface without a thermally activated process in spite of the high barrier property of the oxygen diffusion for the Al_{2}O_{3} layers. In addition, the oxygen radical process at a low process temperature can relatively suppress the diffusion of Ge atoms from the Ge substrate or GeO molecules from the Al_{2}O_{3}/Ge interface to the surface of the Al_{2}O_{3} layer. However, at a high process temperature, Ge atoms and/or GeO molecules actively diffuse into the Al_{2}O_{3} layer during the oxygen radical process as well as the O_{2} thermal annealing, and the diffusion changes the depth distribution of Ge oxides in the Al_{2}O_{3}/Ge structure. From the analysis of the electrical properties of MOS capacitors, the interface state density (D_{it}) of the Al_{2}O_{3}/Ge structure decreases not with increasing thickness of the Ge oxide interlayer but with the amount of Ge oxide near the Al_{2}O_{3}/Ge interface. The increase in the amount of the Ge oxide distributed in the Al_{2}O_{3} layer induces the increase in the capacitance equivalent thickness (CET). The diffusion of Ge into the Al_{2}O_{3} layer with a high process temperature causes the unexpected increase in CET. Therefore, the oxygen radical process at low temperature effectively decreases D_{it} of Al/Al_{2}O_{3}/Ge MOS capacitors without increasing CET.

Heat-Resistant Co–W Catalytic Metals for Multilayer Graphene Chemical Vapor Deposition

2013-04-22T09:00:00+09:00

Authors: Kazuyoshi Ueno, Yusuke Karasawa, Satoru Kuwahara, Shotaro Baba, Hitoshi Hanai, Yuichi Yamazaki, Naoshi Sakuma, Akihiro Kajita, and Tadashi Sakai
Multilayer graphene (MLG) is expected to be a low-resistance and high-reliability interconnect material replacing copper (Cu) in nanoscale interconnects. Chemical vapor deposition (CVD) on catalytic metals is expected as a practical method for MLG deposition. To obtain high-quality MLG films without catalyst agglomeration by CVD, heat-resistant Co–W catalytic metals were investigated. The agglomeration of the Co–W catalytic metals was suppressed by increasing the W composition; however, MLG deposition was suppressed at the same time. The effects of W addition on the MLG growth were discussed from the viewpoints of the crystallographic change of the Co–W catalysts and chemical reactions. It was found that the Co grain size was reduced and the fcc Co formation was suppressed by W addition. In addition, graphite formation was supposed to be suppressed by W addition owing to the formation of phases other than fcc Co according to the Co–W–C phase diagram. With the optimum W concentration, MLG crystallinity was improved by high-temperature CVD using the heat-resistant Co–W catalytic metals (0.7 at. %) without agglomeration, compared with that in the case of using pure-Co catalysts.

Development of Cu/Insulation Layer Interface Crack Extension Simulation with Crystal Plasticity

2013-04-22T09:00:00+09:00

Authors: Kozo Koiwa, Masaki Omiya, Nobuyuki Shishido, Shoji Kamiya, Hisashi Sato, Masahiro Nishida, Takashi Suzuki, Tomoji Nakamura, Toshiaki Suzuki, and Takeshi Nokuo
A novel scheme for the evaluation of interface adhesion energy was examined by a detailed numerical simulation of interface crack extension. The effects of crystal orientation on the Cu/SiN interface adhesion strength of LSI was evaluated using the finite element method. Crack extension simulation was conducted with a model of the actual specimen used for the interface fracture test. The characteristics of elastic–plastic deformation, which changes significantly depending on crystal orientation, were taken into account in the model. With this scheme, the effect of orientation of single crystals on the maximum load P_{max} was investigated under the condition of a constant bonding energy of the interface at the beginning of unstable crack propagation during the fracture test. The values of P_{max} obtained with a number of different crystal orientations ranged over 179–311 µN. The result indicates that the crack propagates more easily in the case that slip deformation of Cu near the interface starts with a low stress, as in the case of the (111) surface. It implies that the apparent interface adhesion strength represented by the load required to debond the interface strongly depends on Cu crystal orientation, because the amount of energy used for plastic deformation of the Cu crystal changes with crystal orientation near the interface.

Growth of Dense, Vertical and Horizontal Graphene and Its Thermal Properties

Akio Kawabata, Tomo Murakami, Mizuhisa Nihei, and Naoki Yokoyama — 2013-04-22T09:00:00+09:00

Authors: Akio Kawabata, Tomo Murakami, Mizuhisa Nihei, and Naoki Yokoyama
We have grown an extremely dense nanocarbon structure on a Si substrate at a temperature of 450 °C, in which vertical graphene layers were formed densely below horizontal graphene layers. We named this carbon structure “dense, vertical, and horizontal graphene (DVHG)”. The density of this structure was an extremely high at 1.4 g/cm^{3}, which is 63% of that of graphite (2.2 g/cm^{3}). Although DVHG showed poor thermal properties, we confirmed that vertical thermal conductivity increased by a factor of 10 by removing the horizontal graphene layers from the top of DVHG. This result indicates that the thermal conductivity parallel to the graphene plane is several orders of magnitude higher than that perpendicular to the graphene plane.

High-Current Reliability and Growth Conditions of Multilayer Graphene Wire Obtained by Annealing Sputtered Amorphous Carbon

2013-04-22T09:00:00+09:00

Authors: Motonobu Sato, Makoto Takahashi, Haruhisa Nakano, Takayuki Muro, Yuji Takakuwa, Shintaro Sato, Mizuhisa Nihei, and Naoki Yokoyama
We fabricated multilayer graphene directly on SiO_{2} by annealing of sputtered amorphous carbon under a catalyst layer without complicated transfer processes, and investigated the effects of the catalysts and the annealing ambient gases on obtaining large-grain, multilayer graphene. As a result, it was found that annealing conditions with a Co catalyst layer in a nitrogen gas atmosphere are important for increasing the ratio of oriented graphene sheets, corresponding to a lower resistivity of the film. Furthermore, it was confirmed that the multilayer graphene wire obtained by optimizing the growth conditions can sustain a high current density of 10^{7} A/cm^{2}, that is, the lifetime of the multilayer graphene wire is over two orders of magnitude longer than that of a Cu wire with the same current density; this current density is over one order of magnitude higher than the current density that can be carried by a Cu wire for the same lifetime.

Sub-Micron-Accuracy Gold-to-Gold Interconnection Flip-Chip Bonding Approach for Electronics–Optics Heterogeneous Integration

2013-04-22T09:00:00+09:00

Authors: Bui Thanh Tung, Motohiro Suzuki, Fumiki Kato, Shunsuke Nemoto, Naoki Watanabe, and Masahiro Aoyagi
High-precision integration has valuable meaning in heterogeneous convergent technology. In this paper we report on a new high-precision low-temperature bonding approach, capable of submicron alignment accuracy, based on the conventional ultrasonic flip-chip bonding technique and modified metal pad and bump elements. The interconnection pair made from a conductive-sloped hollow bonding pad (concave) and metal cone bump (convex) elements, i.e., misalignment self-correction elements, helps in aligning and maintaining the alignment between the chip and the substrate during stacking. By this method, the stacking accuracy can be improved significantly and effectively. Repeatable submicron (i.e., less than 500 nm) bonding accuracies are confirmed through experimental investigation. Moreover, reliable bond characteristics including electrical and mechanical properties are observed, validating the performance of the bonding approach. With these results, the proposed high-precision low-temperature bonding approach shows its suitability for heterogeneous electronics–optics integration applications.

Reductant-Assisted Self-Assembly with Cu/Sn Microbump for Three-Dimensional Heterogeneous Integration

2013-04-22T09:00:00+09:00

Authors: Yuka Ito, Takafumi Fukushima, Kang-Wook Lee, Koji Choki, Tetsu Tanaka, and Mitsumasa Koyanagi
To establish liquid-assisted assembly processes applicable to heterogeneous system integrations, we present flip-chip self-assembly of dies with Cu/Sn microbumps using the difference in droplet wetting between hydrophilic and hydrophobic areas. Flip-chip self-assembly is assisted by a water-soluble flux that has high surface tension comparable to that of pure water and contains an additive of a reducing agent for metal oxides. Control of the additive concentration in the flux provides high wettability contrast that enable spontaneous and precise alignment of chips to hydrophilic areas formed on substrates within 5 µm in alignment accuracy. In the subsequent chip bonding process, the reductant can eliminate the metal oxide layer and improve the solder wettability of Sn to the corresponding electrode pads formed on the chips. In addition, we confirm, through electrical characteristic evaluation after thermal compression bonding, that the resulting daisy chain formed between the substrates and self-assembled chips with the flux shows sufficiently low contact resistance of below 20 mΩ/bump without disconnection.

Room-Temperature Cu Microjoining with Ultrasonic Bonding of Cone-Shaped Bump

Lijing Qiu, Akihiro Ikeda, Kazuhiro Noda, Seiya Nakai, and Tanemasa Asano — 2013-04-22T09:00:00+09:00

Authors: Lijing Qiu, Akihiro Ikeda, Kazuhiro Noda, Seiya Nakai, and Tanemasa Asano
Room-temperature Cu–Cu bonding was realized by applying ultrasonic vibration together with compression force to the bonding of a cone-shaped bump. The size of the bump was about 10 µm. The connection pitch was 20 µm. Mechanical characterization showed that the bonding strength increases with vibration amplitude and depends on the thickness of the counter electrode made of Cu. The thickness dependence of the bonding strength was found to be caused by an increase in the surface roughness of the counter electrode. It was shown that the bonding strength meets the requirement from application to products. Electrical characterization using a daisy-chain connection test demonstrated that more than 10,000 pins on a chip can be connected with a sufficiently low resistance.

Investigation of Local Bending Stress Effect on Complementary Metal–Oxide–Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

2013-04-22T09:00:00+09:00

Authors: Hisashi Kino, Ji Choel Bea, Mariappan Murugesan, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi, and Tetsu Tanaka
A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal–oxide–semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal–oxide–semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip.

Tunnel Field-Effect Transistor with Epitaxially Grown Tunnel Junction Fabricated by Source/Drain-First and Tunnel-Junction-Last Processes

2013-04-22T09:00:00+09:00

Authors: Yukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Meishoku Masahara, and Hiroyuki Ota
We fabricate p- and n-channel Si tunnel field-effect transistors (TFETs) with an epitaxially grown tunnel junction. In a novel source/drain-first and tunnel-junction-last fabrication process, a thin epitaxial undoped Si channel (epichannel) is deposited on a preferentially fabricated p- or n-type source area. The epichannel sandwiched by a gate insulator and a highly doped source well acts as a parallel-plate tunnel capacitor, which effectively multiplies drain current with an enlarged tunnel area. On the basis of its simple structure and easy fabrication, symmetric n- and p-transistor and complementary metal oxide semiconductor inverter operations were successfully demonstrated.

Impacts of Surface Roughness Reduction in (110) Si Substrates Fabricated by High-Temperature Annealing on Electron Mobility in n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on (110) Si

2013-04-22T09:00:00+09:00

Authors: Sung-Ho Jeon, Noriyuki Taoka, Hiroaki Matsumoto, Kiyotaka Nakano, Susumu Koyama, Hiroshi Kakibayasi, Koji Araki, Moriya Miyashita, Koji Izunome, Mitsuru Takenaka, and Shinichi Takagi
The effects of high-temperature Ar/H_{2} annealing on (110) Si, which is known to provide flat (110) Si surfaces, have been studied from the viewpoint of metal–oxide–semiconductor (MOS) interface roughness and inversion-layer electron mobility limited by surface roughness scattering in (110) Si n-channel metal–oxide–semiconductor field-effect transistors (n-MOSFETs). It has been confirmed by quantitative transmission electron microscope (TEM) analysis that the reduction in the surface roughness on (110) Si is still maintained after gate oxidation with gate oxide thickness (T_{ox}) of 6.9 nm. The mobility measurement of (110) Si n-MOSFETs fabricated using Si wafers with high-temperature Ar/H_{2} annealing has revealed that the high-temperature annealing increases the electron mobility of (110) Si MOSFETs at 10 K by 14 and 5.7% for T_{ox} values of 6.9 and 8.9 nm, respectively, and increases the electron mobility at 300 K by 2.5 and 0.72% for T_{ox} values of 6.9 and 8.9 nm, respectively. The T_{ox} dependence of the enhancement factor might be attributable to the increase in MOS interface roughness with increasing T_{ox}. It has also been observed that the mobility enhancement factor is slightly dependent on the channel direction. The mobility increase has been observed to be greater along <111> than along <112>.

Current Enhancement of Green Transistors Compared with Conventional Tunnel Field-Effect Transistors

Min-Hung Lee, Jhe-Cyun Lin, Cheng-Ying Kao, and Chih-Wei Chen — 2013-04-22T09:00:00+09:00

Authors: Min-Hung Lee, Jhe-Cyun Lin, Cheng-Ying Kao, and Chih-Wei Chen
P-type tunneling-based high-driving-current green field-effect transistors (p-gFETs) with dopant segregation (DS) on bulk Si were successfully fabricated and developed. gFETs with the vertical band-to-band tunneling (BTBT) mechanism have a valid benefit for ∼25× ON current enhancement compared with tunneling field-effect transistors (TFETs) without sacrificing leakage current and subthreshold swing for CMOS scaling in future-generation transistors. Ni DS enhanced the amount of n^{+} dopant in the source/drain region and produced a steep junction profile, which improved the BTBT mechanism. The promising gFET with silicon-on-insulator-free (SOI-free) gFET can be compatible with current processes and solve the issues of cost and thermal dissipation.

Influence of Structural Parameters on Electrical Characteristics of Schottky Tunneling Field-Effect Transistor and Its Scalability

2013-04-22T09:00:00+09:00

Authors: Yan Wu, Chunmeng Dou, Feng Wei, Kuniyuki Kakushima, Kenji Ohmori, Parhat Ahmet, Takanobu Watanabe, Kazuo Tsutsui, Akira Nishiyama, Nobuyuki Sugii, Kenji Natori, Keisaku Yamada, Yoshinori Kataoka, Takeo Hattori, and Hiroshi Iwai
The influence of structural parameters, including the Schottky barrier height for electron (φ_{Bn}) and channel doping (N_{a}), on the electrical characteristics of a scaled Schottky barrier tunneling FET (SBTFET) have been clarified by numerical device simulation. The thermionic emission current (I_{TH}) as well as the tunneling current (I_{TN}) have been considered as the main electron injections at the source edge. Simulation results have revealed that the main conduction is I_{TN} in the region near and above the threshold voltage (V_{th}). As tunneling probability is determined by φ_{Bn} and the width of the triangular potential barrier at the source edge, a lower φ_{Bn} with higher N_{a} results in a better subthreshold swing (SS) with high on-state drive current (I_{ON}) at a gate length (L_{g}) of 50 nm. With L_{g} scaling down to 10 nm, however, a lower φ_{Bn} has shown an increased off-state leakage current (I_{OFF}) due to the short-channel effect (SCE), while a larger φ_{Bn} can suppress the I_{OFF} at the cost of I_{ON}. Therefore, considering SS with I_{ON} and I_{OFF} ratio, it can be concluded that an optimum φ_{Bn} exists for short-channel devices. The SBTFET showed good subthreshold performance and higher I_{ON}/I_{OFF} than the conventional silicon-on-insulator (SOI) MOSFET in 10 nm region with the Schottky barrier height optimization.

Analysis and Modeling of Geometry Dependent Thermal Resistance in Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

2013-04-22T09:00:00+09:00

Authors: Xingye Zhou, Takuya Inoue, Masashi Kitamura, Kai Matsuura, Masataka Miyake, Takahiro Iizuka, Takuya Umeda, Hideyuki Kikuchihara, Hans Juergen Mattausch, Jin He, and Mitiko Miura-Mattausch
It is demonstrated that the self-heating effect easily causes elevated thermal equilibrium condition within the active device for thin substrate MOSFETs. This leads to a non-linearity of the thermal resistance, which originally is a material specific constant. A compact model for describing the observed effective nonlinear thermal resistance has been developed which captures the device geometry effects as well as the bias condition dependences.

Novel Field Effect Diode Type Vertical Capacitorless One Transistor Dynamic Random Access Memory Cell with Negative Hold Bit Line Bias Scheme for Improving the Hold Characteristics

Takuya Imamoto and Tetsuo Endoh — 2013-04-22T09:00:00+09:00

Authors: Takuya Imamoto and Tetsuo Endoh
In this paper, the novel field effect diode (FED) type vertical capacitorless one transistor dynamic random access memory (1T-DRAM) cell with negative hold bit line (BL) voltage (V_{BL}) scheme is proposed. In comparison with the conventional planar type, the proposed vertical type with negative hold V_{BL} scheme shows excellent static and disturb retention time. The proposed vertical type memory cell with negative hold V_{BL} scheme achieves 1,000 times longer static retention time and 10^{4} times longer BL disturb retention time at 85 °C than that of the conventional planar type. Furthermore, the proposed vertical type memory cell has a small cell size of 4F^{2} due to its stacked vertical structure. The proposed FED type vertical capacitorless 1T-DRAM cell with negative hold V_{BL} scheme is shown to be an excellent candidate for stand-alone and embedded memory applications and extends scaling limitations.

Squareness Control in Polarization–Electric Field Hysteresis Curves in Rhombohedral Pb(Zr,Ti)O_{3} Films

2013-04-22T09:00:00+09:00

Authors: Akihiro Sumi, Takahiro Oikawa, Hitoshi Morioka, Shoji Okamoto, Shintaro Yokoyama, Takayuki Watanabe, Yoshitaka Ehara, and Hiroshi Funakubo
Squareness in polarization–electric field hysteresis loops of (100)-oriented epitaxial and fiber-textured rhombohedral Pb(Zr,Ti)O_{3} films prepared on (100) SrTiO_{3} and (100) Si substrates, respectively, was investigated as a function of temperature. The ratio of remanent polarization to saturation polarization (P_{r}/P_{sat}) decreased with increasing temperature for all films. It depends on the kind of substrates and the remained strain in the in-plane orientation. These data suggest that the existing strain in the films possibly affects the temperature dependence of the P_{r}/P_{sat} ratio.

Filament Evolution during Set and Reset Transitions in Oxide Resistive Switching Memory

Daniele Ielmini, Simone Balatti, and Stefano Larentis — 2013-04-22T09:00:00+09:00

Authors: Daniele Ielmini, Simone Balatti, and Stefano Larentis
Bipolar resistive switching memory (RRAM) relies on ion migration effects taking place at a conductive filament (CF). Understanding the evolution of the CF during set and reset transitions is essential for predicting RRAM scalability and for developing new methods for storage and computation. This work describes the evolution of the CF during bipolar resistive switching through numerical simulations of ion drift/diffusion. The defect distribution profile for increasing current after set transition and for increasing voltage during set transition are shown. Finally, the asymmetric shape of the CF is evidenced through polarity-dependent experiments and explained through numerical simulations.

Physical Guiding Principles for High Quality Resistive Random Access Memory Stack with Al_{2}O_{3} Insertion Layer

2013-04-22T09:00:00+09:00

Authors: Moon Young Yang, Katsumasa Kamiya, Blanka Magyari-Köpe, Hiroyoshi Momida, Takahisa Ohno, Masaaki Niwa, Yoshio Nishi, and Kenji Shiraishi
We theoretically clarified the atomistic role of the Al_{2}O_{3} oxygen vacancy (V_{O}) barrier layer in advanced ReRAM stacks. We found that V_{O} filament formation in Al_{2}O_{3} can be controlled by applying voltage when the Al_{2}O_{3} layer is in contact with V_{O} source layer such as Hf, although V_{O} formation in Al_{2}O_{3} is difficult in usual situation. Moreover, we proposed a physical guiding principle toward designing high quality ReRAM stacks with Al_{2}O_{3} V_{O} barrier layers.

Forward and Reverse Biasing in Resistive Memories for Fast, Disturb-Free Read, and Verify

Tomoko Ogura Iwasaki, Sheyang Ning, and Ken Takeuchi — 2013-04-22T09:00:00+09:00

Authors: Tomoko Ogura Iwasaki, Sheyang Ning, and Ken Takeuchi
The potential of resistive random access memory (ReRAM) to provide high speed operation is held back by the need to verify during set/reset, and sensitivity to read disturb. 50 nm HfO_{2} cells are measured for disturb in forward and reverse directions, and at 25 and 85 °C. Two circuit proposals provide speed and reliability improvement. First, bipolar verify reduces write time. If the verify direction matches the set/reset direction, read voltage can be increased, which reduces signal development time, and eliminates the need to switch the highly capacitive source line voltage. Secondly, reverse read with dynamic write-back provides fast, disturb-free read. A margin-check is performed in parallel to normal reverse-read. Disturb of the low resistance state is monitored, and then, if needed, set write-back occurs. Based on disturb data, write-back occurs infrequently, after ∼5×10^{9} reads. By these two proposals, write time can be reduced by 3× and 5× faster read with disturb immunity can be achieved.

Improved Memory Characteristics of A Novel TaN/Al_{2}O_{3}/TiO_{2}/HfO_{2}/SiO_{2}/Si Structured Charge Trapping Memory

Yahua Peng, Fei Liu, Xiaoyan Liu, Gang Du, and Jinfeng Kang — 2013-04-22T09:00:00+09:00

Authors: Yahua Peng, Fei Liu, Xiaoyan Liu, Gang Du, and Jinfeng Kang
In this work, we evaluate the program/erase/retention performance of a novel TaN/Al_{2}O_{3}/TiO_{2}/HfO_{2}/SiO_{2}/Si (TATHOS) charge trapping memory (CTM) device with the stacked HfO_{2}/SiO_{2} tunneling layer and TiO_{2} charge trapping layer by our developed simulator, which has included the critical mechanisms in CTM and has been verified with the experiment data. With various gate dielectric layer's thicknesses and materials, bias voltages and temperatures, the novel structure device's performance are studied and compared to some conventional devices. It can been seen that with appropriate design for the stack tunneling layer and TiO_{2} choice for the charge trapping layer, significantly improved program/erase speed and retention characteristics could be achieved. It can be a useful tool to optimize the performance of CTM with the gate layer materials' choice and design.

Research of Bulk Erase Operation in Vertical Three-Dimensional Cell Array Architecture

Hyung-jun Yang, Gae-hun Lee, Kyeong-rok Kim, and Yun-heub Song — 2013-04-22T09:00:00+09:00

Authors: Hyung-jun Yang, Gae-hun Lee, Kyeong-rok Kim, and Yun-heub Song
A bit-cost scalable (BiCS) NAND flash memory with a bulk erasing method is investigated in view of cell characteristics and uniformity. The proposed cell array has an additional electrode layer for a bulk erase operation in the middle of a vertical channel string cell. Here, under a bias condition of 20 V, a programming threshold voltage of 4.2 V at 1 ms and an erasing threshold voltage of V_{th} = -1.5 V at 10 ms are confirmed, which is acceptable for flash memories. Furthermore, the shielding transistor close to an erase electrode is also investigated, which gives better erase characteristics for the cells adjacent to the erase electrode. From this result, we expect that a bulk erasable-BiCS technology with a shielding transistor can be a candidate three-dimensional (3D) NAND flash memory.

A Programmable Difference-of-Gaussian Analog Complementary Metal Oxide Semiconductor Image Sensor Operating in the Subthreshold Regime

Zheye Wang and Tadashi Shibata — 2013-04-22T09:00:00+09:00

Authors: Zheye Wang and Tadashi Shibata
A difference-of-Gaussian (DoG) analog CMOS image sensor architecture in which the kernel size and shape are made arbitrarily programmable has been developed based on the MOS subthreshold characteristics. The variability of MOS transistor threshold voltage causes a serious problem in the circuits operating in the subthreshold regime because the current varies exponentially depending on the threshold voltage. The problem has been alleviated by introducing a cancellation scheme employing a switched floating-gate MOS (neuMOS) circuitry. A proof-of-concept chip was designed in a 0.18-µm CMOS technology. The operation of the designed circuits was investigated by SPICE (simulation program with integrated circuit emphasis) simulation and their basic functions were demonstrated. A part of the core function, i.e., the generation of the Gaussian function profile, was confirmed by the measurement of a fabricated test circuit.

False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

Takuya Sawada, Hidehiro Takata, Koji Nii, and Makoto Nagata — 2013-04-22T09:00:00+09:00

Authors: Takuya Sawada, Hidehiro Takata, Koji Nii, and Makoto Nagata
Static random access memory (SRAM) cores exhibit susceptibility against power supply voltage variation. False operation is investigated among SRAM cells under sinusoidal voltage variation on power lines introduced by direct RF power injection. A standard SRAM core of 16 kbyte in a 90 nm 1.5 V technology is diagnosed with built-in self test and on-die noise monitor techniques. The sensitivity of bit error rate is shown to be high against the frequency of injected voltage variation, while it is not greatly influenced by the difference in frequency and phase against SRAM clocking. It is also observed that the distribution of false bits is substantially random in a cell array.

Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator

2013-04-22T09:00:00+09:00

Authors: Sho Ikeda, Sang-yeop Lee, Tatsuya Kamimura, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu
In this paper, we present a fractionally injection-locked frequency multiplication technique that can solve the tradeoff between the selectable frequency step and phase noise of injection-locked frequency multipliers (ILFMs). For a given output frequency step, the phase noise of the proposed ILFM is lower than that of conventional ILFMs because higher-frequency signals can be injected. The proposed ILFM was fabricated using a 180 nm Si complementary metal oxide semiconductor (CMOS) process. 1/2-, 1/3-, 1/4-, and 1/6-integral frequency multiplications were realized, which means that the output frequency resolution is 6 times as high as that of conventional ILFM. When the reference frequency was 100 MHz, the measured phase noise at 725 (= 100×29/4) MHz was -120 dBc/Hz at a 1 MHz offset, and that at 767 (= 100×23/3) MHz was -119 dBc/Hz at 1 MHz offset.

Mechanism Study of Gate Leakage Current for AlGaN/GaN High Electron Mobility Transistor Structure Under High Reverse Bias by Thin Surface Barrier Model and Technology Computer Aided Design Simulation

2013-04-22T09:00:00+09:00

Authors: Kazuo Hayashi, Yutaro Yamaguchi, Toshiyuki Oishi, Hiroshi Otsuka, Koji Yamanaka, Masatoshi Nakayama, and Yasuyuki Miyamoto
Gate leakage current mechanism in GaN high electron mobility transistors (HEMTs) has been studied using a two-dimensional thin surface barrier (TSB) model to represent two unintentional donor thin layers that exit under and outside the gate electrode due to the existence of surface defects. The donor thin layer outside the gate affects the reverse gate current at the high gate voltage above the pinch-off voltage. Higher donor concentration of thin layer outside the gate results in larger ratio of lateral to vertical components of the electric field at the gate edge. On the other hand, the electric field at the center of the gate has only the vertical electric field component. As a result, the two-dimensional effects are only important for the reverse gate current above the pinch-off voltage. We have confirmed in this paper that the simulation results provided by our model correlate very well with the experimental reverse gate current characteristics of the device for a very wide range of reverse gate voltage from 0.1 to 90 V.

Characterization of Electroluminescence from One-Dimensionally Self-Aligned Si-Based Quantum Dots

Hiroki Takami, Katsunori Makihara, Mitsuhisa Ikeda, and Seiichi Miyazaki — 2013-04-22T09:00:00+09:00

Authors: Hiroki Takami, Katsunori Makihara, Mitsuhisa Ikeda, and Seiichi Miyazaki
We have demonstrated self-assembling formation of one-dimensionally self-aligned Si-based quantum dots (QDs) structures and applied them to an active layer of light emitting diodes (LEDs) with a semitransparent Au gate. Under forward bias conditions over threshold biases as low as ∼1.2 and ∼-2.0 V for LEDs formed on n- and p-Si(100), respectively, stable electroluminescence (EL) was observable in the near-infrared region at room temperature. The observed EL spectra could be deconvoluted into mainly two component peaks at ∼1140 and ∼1100 nm that originated from lower and upper dots, respectively, where both spectrum intensities showed a power-law relationship of the EL intensity with applied bias and input power. Notice that the slope of the component peak for the lower dots was larger than that for the upper dots, indicating that holes were stably stored in the lower dots due to a deep potential well. In fact, when an AC bias as low as ∼6.4 V (DC at 2.0 V) was applied to the LEDs with an Au gate formed on the n-Si(100), a single component peak for the lower dots was detected, indicating electron–hole recombination in the lower dots caused by alternate carrier injection from the Si(100) substrate.

Strongly Enhanced Four-Wave Mixing Signal from GaAs/AlAs Cavity with InAs Quantnm Dots Embedded in Strain-Relaxed Barriers

Yukinori Yasunaga, Hyuga Ueyama, Ken Morita, Takahiro Kitada, and Toshiro Isu — 2013-04-22T09:00:00+09:00

Authors: Yukinori Yasunaga, Hyuga Ueyama, Ken Morita, Takahiro Kitada, and Toshiro Isu
Strong ultrafast four-wave mixing signals at ∼1.5 µm were demonstrated in a GaAs/AlAs multilayer cavity containing self-assembled InAs quantum dots (QDs) embedded in strain-relaxed In_{0.35}Ga_{0.65}As barriers. Time-resolved optical measurements using 100 fs pulses with 100 kHz repetition rate were carried out in the various excitation powers at room temperature. Strongly enhanced four-wave-mixing signals were observed for a cavity with two InAs QDs layers inserted in a half-wavelength (λ/2) cavity layer compared with that of a GaAs λ/2 cavity that had no QDs, in the whole range of excitation power (0.3–2 mW). For a low excitation power below 0.6 mW, the four-wave-mixing signals were about two orders of magnitude larger than that of the GaAs λ/2 cavity owing to the large nonlinearity of the InAs QDs.

Si Waveguide-Integrated Metal–Semiconductor–Metal and p–i–n-Type Ge Photodiodes Using Si-Capping Layer

2013-04-22T09:00:00+09:00

Authors: Junichi Fujikata, Makoto Miura, Masataka Noguchi, Daisuke Okamoto, Tsuyoshi Horikawa, and Yasuhiko Arakawa
We studied Si waveguide-integrated metal–semiconductor–metal (MSM) and p–i–n-type Ge photodiodes (Ge-PDs), using a Si-capping layer. As for an MSM Ge-PD, the Schottky barrier height was increased up to 0.44 V by applying a 8–20 nm Si-capping layer, and a very low dark current density of approximately 0.4 nA/µm^{2} was achieved with a high responsivity of 0.8 A/W. In addition, a small electrode spacing of 1 µm realized high-speed photodetection of 20 Gbps. As for a p–i–n-type Ge-PD, by applying a 10–20 nm Si capping layer, the contact resistance between a metal electrode of Ti/TiN/Al and n^{+}-Si capping layer was successfully reduced to 1×10^{-5} Ω·cm^{2}. A 45 GHz bandwidth was obtained with a low dark current density of 0.8 nA/µm^{2}. Moreover, a more than 20 GHz bandwidth was achieved with zero-bias voltage. In the case of zero-bias voltage operation, a 3 dB bandwidth was a little affected by input power, which would originate from the photocarrier screening effect on the built-in electric field.

Single Photon Generation from an Impurity Center with Well-Defined Emission Energy in GaAs

2013-04-22T09:00:00+09:00

Authors: Liao Zhang, Michio Ikezawa, Tatsuya Mori, Shintaro Umehara, Yoshiki Sakuma, Kazuaki Sakoda, and Yasuaki Masumoto
We studied optical properties of isoelectronic traps in nitrogen δ-doped GaAs by micro-photoluminescence (µ-PL) spectroscopy. We found that these nitrogen impurity centers (NN_{A}) emit photons with nearly identical emission energy at 1475 meV and polarization direction. Furthermore, single photon generation from a single impurity center was confirmed by a strong photon antibunching under the continuous optical excitation at 5 K. Our results suggest that the nitrogen impurity center in GaAs might be well suited for the energetically-defined single photon source for the quantum information application.

Complementary Metal Oxide Semiconductor-Compatible Back-Side-Illuminated Photodiode for Optoelectronic Integrated Circuit Devices

Sang-Baie Shin, Hiroto Sekiguchi, Hiroshi Okada, and Akihiro Wakahara — 2013-04-22T09:00:00+09:00

Authors: Sang-Baie Shin, Hiroto Sekiguchi, Hiroshi Okada, and Akihiro Wakahara
In this study, the prototype optoelectronic integrated circuits (OEICs) operating with optical input signals were designed and fabricated. A back-side-illuminated (BSI) photodiode was designed and demonstrated by a newly proposed practical method, utilizing micro-electromechanical systems (MEMS) and postcomplement metal oxide semiconductor (CMOS) processes. Additional fabrication processes for the BSI photodiode were proposed and described in detail in this paper. The operational amplifier for amplification of the optical current by the BSI photodiode as the transimpedance amplifier was designed and fabricated. And the pulse width modulation (PWM) wave generator was implemented for modulating optical signals as the prototype OEIC device. The maximum quantum efficiency of 28.4% was obtained from the fabricated BSI photodiode. Output signals of PWM were successfully controlled by the generated optical current of the BSI photodiode.

Gain Measurement of Highly Stacked InGaAs Quantum Dot Laser with Hakki–Paoli Method

Fumihiko Tanoue, Hiroharu Sugawara, Kouichi Akahane, and Naokatsu Yamamoto — 2013-04-22T09:00:00+09:00

Authors: Fumihiko Tanoue, Hiroharu Sugawara, Kouichi Akahane, and Naokatsu Yamamoto
A 147-µm-long cavity laser diode with 19 InGaAs quantum dot layers was fabricated by the ultrahigh-rate molecular beam epitaxial growth technique, and its gain properties were investigated using the Hakki–Paoli method below the threshold current (I_{th}) of 111.5 mA. At an injection current of 100.3 mA (0.9I_{th}), the positive net modal gain was in the range between 1005 and 1043 nm, corresponding to a photon energy of 45 meV. The maximum net modal gain and maximum modal gain were 46.5 and 60.5 cm^{-1}, respectively. A differential net modal gain of as high as 3.8 cm^{-1}/mA was observed at 0.77 times the threshold current. No gain saturation appeared below the threshold current, and injection currents higher than 78.4 mA (≈0.7I_{th}) were required to obtain a net modal gain.

Output Characteristics of a Semiconductor Laser Diode with Double Ring Cavities and a Y-Junction Coupler

Ming Chang Shih, Yu Chin Sun, and Shin Wei Fan — 2013-04-22T09:00:00+09:00

Authors: Ming Chang Shih, Yu Chin Sun, and Shin Wei Fan
We demonstrated an InGaAlP multiple-quantum-well semiconductor laser diode with double circular ring cavities and its output characteristics. It was found that the optical confinement factor of the ridge waveguide plays an important role in the output emission of this device, and superluminescence emission can be achieved with a low-confinement ridge waveguide. Spatial solitons can be generated in the ridge waveguide of 8 µm width and 0.9 µm depth owing to a nonlinear photorefractive effect. When the injection current in the circular ring cavity increases, the feedback light from the Y-junction coupling section continuously enhances the excitation through the soliton waveguide. In addition, the double-ring cavities provide wavelength filtering and feedback control from the Y-junction coupling section to achieve a superluminescent mode or lasing mode output operation. Results of light–current (L–I) and spectral measurements of the devices with various waveguide properties were presented to explore the mechanism of the output from this circular ring laser diode.

Luminescence Properties of Rare-Earth-Doped Thiosilicate Phosphors on Silicon Substrate

Yasushi Nanai, Yu Sakamoto, and Tsuyoshi Okuno — 2013-04-22T09:00:00+09:00

Authors: Yasushi Nanai, Yu Sakamoto, and Tsuyoshi Okuno
The luminescence properties of rare-earth-doped thiosilicate phosphors are reported. These thiosilicate materials are fabricated in phosphor layers on silicon substrates. For Eu^{2+}-doped calcium thiosilicate, yellow (560 nm) and red (650 nm) bands are obtained in the photoluminescence spectrum, which is almost the same as that for the corresponding powder sample. The energy transfer efficiency from Eu^{2+} to Er^{3+} in Eu_{2}SiS_{4}:Er^{3+} on Si substrates is improved by optimization of the annealing conditions. In addition, the insulation of electroluminescence devices using BaSi_{2}S_{5}:Eu^{2+} on silicon-on-insulator substrates is improved using a high-dielectric-constant polymer as a transparent insulating layer.

Band-Edge Electronic Structure and Pre-existing Defects in Remote Plasma Deposited Non-crystalline SiO_{2} and GeO_{2}

Gerald Lucovsky — 2013-04-22T09:00:00+09:00

Authors: Gerald Lucovsky
The following topics are addressed: (i) X-ray absorption spectroscopy (XAS) studies of plasma deposited non-crystalline (nc-) SiO_{2} and GeO_{2} emphasizing (a) band-edge states and (b) pre-existing bonding defects, and (ii) interpretation of X-ray absorption and photoemission spectra based on many electron theory, including two-electron singlet and triplet electron spin states. The articles also addresses electronic and defect structures in emerging device structures incorporating (GeO_{2})_{x}(SiO_{2})_{1-x} alloys, and bonding between Ge and Si substrates and elemental and/or alloy nc-SiO_{2} and nc-GeO_{2}. The most significant results are identification of local atomic structure of pre-existing defects in the elemental oxides. Defects are created during processing, and are qualitatively different than those produced by X-ray, γ-ray, or high energy electron stressing and detected by second derivative XAS.

A Comprehensive Study on the Optical Properties of Thin Gold-Doped Rhenium Disulphide Layered Single Crystals

2013-04-22T09:00:00+09:00

Authors: Chih-Cheng Huang, Chen-Chia Kao, Der-Yuh Lin, Chih-Ming Lin, Fan-Lei Wu, Ray-Hua Horng, and Ying-Sheng Huang
We present a comprehensive study on the optical properties of gold-doped rhenium disulphide (ReS_{2}:Au) layer crystal. Its anisotropic optical properties were studied by using the polarization-dependent optical absorption and photoconductivity (PC) measurements. Absorption measurements indicate that the absorption edge shifted toward high energy as the sample was slimmed down to a thin piece. For the first time, excitonic transitions have been observed by this method. The room temperature transition energies were evaluated to be 1.48 eV for E_{1}^{ex} and 1.516 eV for E_{2}^{ex}. E_{1}^{ex} exciton dominates the transition as the polarization is parallel to the b-axis of the layer crystal, while E_{2}^{ex} exciton is most present as the polarization is perpendicular. PC spectra are performed to check this anisotropic phenomenon. Thermoreflectance modulation (TR) and photoluminescence (PL) measurements have been performed in the temperature range of 42 to 300 K. The temperature dependence of the transition energies and broadening parameters were determined.

Performance Revelation and Optimization of Gold Nanocrystal for Future Nonvolatile Memory Application

Chih-Ting Lin, Jer-Chyi Wang, Po-Wei Huang, Yu-Yen Chen, and Li-Chun Chang — 2013-04-22T09:00:00+09:00

Authors: Chih-Ting Lin, Jer-Chyi Wang, Po-Wei Huang, Yu-Yen Chen, and Li-Chun Chang
The annealing effects on the gold nanocrystal (Au-NC) formation for memory application are proposed. At higher annealing temperatures, the memory window becomes larger owing to the high density of Au-NCs. The average size of the Au-NCs is approximately 5 nm, and the spaces between NCs tend to decrease with annealing temperature. Furthermore, the retention charge loss rate was optimized at 700 °C annealing formation and found to be dominated by the thermally activated and tunneling mechanisms. The high charge loss rate for the thermally activated mechanism shows no dependence on annealing temperature, while the low charge loss rate for the tunneling depends on the spaces between NCs. Besides, the activation energy of the thermally activated electron loss was low at a high Au-NC density, which can be attributed to the lateral electron migration between NCs. The endurance of the 700 °C annealed sample can sustain a memory window of approximately 1.1 V after 10^{4} program/erase cycles.

Impact of Illumination on Charge Injection and Accumulation in Organic Transistor in Presence of Plasmonic Nanoparticles

2013-04-22T09:00:00+09:00

Authors: Keanchuan Lee, Martin Weis, Xiangyu Chen, Dai Taguchi, Takaaki Manaka, and Mitsumasa Iwamoto
Effects of illumination on the carrier injection and transport due to photogenerated carriers were investigated in pentacene organic field-effect transistor (OFET). A plasmonic nanoparticles self-assembled monolayer (SAM) was incorporated in pentacene FET to act to enhance the photo-carrier generation. The influence of nanoparticles (NPs) on the photogeneration as well as on the charge trapping has been investigated using the current–voltage (I–V) and impedance spectroscopy (IS) measurements. The I–V results proved higher amount of photogenerated charge in presence of NPs even though this device has the contact resistance about two orders higher and effective mobility an order lower than the reference device without plasmonic NPs. The IS analysis of relaxation times verified strong influence of NPs on the charge trapping.

Transparent Organic Thin Film Transistors Using an Oxide/Metal/Oxide Trilayer as Low-Resistance Transparent Source/Drain Electrodes

Shui-Hsiang Su, Chung-Ming Wu, Hsiang-Lin Tsai, and Meiso Yokoyama — 2013-04-22T09:00:00+09:00

Authors: Shui-Hsiang Su, Chung-Ming Wu, Hsiang-Lin Tsai, and Meiso Yokoyama
This work presents transparent pentacene-based organic thin film transistors (OTFTs) in which an oxide/metal/oxide trilayer provides low-resistance transparent source/drain electrodes. The device structure is glass/indium–tin oxide (ITO)/poly(methyl methacrylate) (PMMA)/pentacene/transparent source–drain electrode. The transparent source/drain electrode consists of a low-resistance metal, silver, that is sandwiched by a high-transmittance oxide, WO_{3}. The structure of the transparent source–drain electrode is optimized by tuning the thickness of each layer. The optimized structure has a sheet resistance of 6.2 Ω/sq. and an optimum transmittance of 70% in the visible wavelength range of 380–780 nm. The pentacene-based OTFT employing optimized transparent source–drain electrode yields an output current (I_{DS}) of -7.08 µA, a field-effect mobility (µ) of 0.22 cm^{2} V^{-1} s^{-1}, an on–off drain current ratio of 1.8×10^{5}, and a threshold voltage of -15.1 V. OTFTs in which WO_{3} (5 nm)/Ag (10 nm)/WO_{3} (30 nm) is used as the source/drain electrode greatly outperform OTFTs in which silver is utilized, because the work function of WO_{3}/Ag/WO_{3} substantially exceeds that of silver.

Synthesis and Physical Vapor Deposition of Low-Molecular-Weight Poly(3,4-ethylenedioxythiophene)

2013-04-22T09:00:00+09:00

Authors: Taikai Eguchi, Yuusuke Tsuchiya, Ai Hasegawa, Kuniaki Tanaka, Kenji Ogino, and Hiroaki Usui
Thin films of poly(3,4-ethylenedioxythiophene) (PEDOT) were obtained by physical vapor deposition. To this end, low-molecular-weight PEDOT was synthesized by oxidative polymerization using oxygen as the oxidizing reagent with palladium acetate and copper acetate as the catalysts. The degree of polymerization was controlled by adjusting reaction time. The material can be vapor-deposited by thermal evaporation when the degree of polymerization was about 10. Formation of PEDOT thin films was confirmed by infrared spectroscopy. The optical absorption edge of the deposited film showed a redshift with increasing degree of polymerization. The electrical conductivity of the deposited film was in the range from 10^{-4} to 10^{-3} S/cm. The deposited films are expected to be in the nondoped state since the oxidizing reagent (oxygen) is unlikely to remain in the films.

Ultrathin Poly(4-vinylphenol) Interfacial Layer Evaporation for Low-Voltage Operation of Organic Field-Effect Transistors with HfO_{2} Gate Insulator

Shun-ichiro Ohmi, Kousuke Kamino, and Hiroshi Ishiwara — 2013-04-22T09:00:00+09:00

Authors: Shun-ichiro Ohmi, Kousuke Kamino, and Hiroshi Ishiwara
Ultrathin poly(4-vinylphenol) (PVP) layer formation by evaporation was investigated for the first time to improve the pentacene/HfO_{2} interface characteristics in bottom-gate organic field-effect transistors (OFETs). 3–10-nm-thick PVP layers were successfully deposited by evaporation. It was found that the surface roughness of the PVP layer was remarkably decreased at the deposition temperatures of 50–100 °C both on SiO_{2} and HfO_{2} gate insulators. The obtained relative dielectric constants of the PVP layers deposited on SiO_{2} and HfO_{2} were 3.4 and 4.8, respectively. The mobility in the fabricated pentacene-based p-type OFETs with the HfO_{2} gate insulator was increased from 0.25 cm^{2} to 0.32 cm^{2} V^{-1} s^{-1} at the operation voltage of 2 V by the 5-nm-thick PVP interfacial layer deposited at 50 °C.

Fabrication and In vivo Evaluation of Poly(3,4-ethylenedioxythiophene) Stimulus Electrodes for Fully Implantable Retinal Prosthesis

2013-04-22T09:00:00+09:00

Authors: Chikashi Kigure, Hideki Naganuma, Yuichiro Sasaki, Hisashi Kino, Hiroshi Tomita, and Tetsu Tanaka
The development of poly(3,4-ethylenedioxythiophene) (PEDOT) stimulus electrodes and the relationship between the electrical stimulation of a rabbit retina and electrically evoked potential (EEP) were studied in detail. We fabricated implantable flexible cables with Pt, IrO_{x}, and PEDOT electrodes and evaluated the electrochemical impedances (EIs) and charge injection capacities (CICs) of such electrodes. From the result, we confirmed that PEDOT electrodes have both lower EIs and larger CICs than Pt and IrO_{x} electrodes. In addition, we performed in vivo experiments with PEDOT electrodes and clarified the relationships between the electrical stimulation of the rabbit retina and EEP. It is highly probable that visual restoration will be realized safely with PEDOT electrodes.

Study of Insertion Characteristics of Si Neural Probe with Sharpened Tip for Minimally Invasive Insertion to Brain

Sanghoon Lee, Soichiro Kanno, Hisashi Kino, and Tetsu Tanaka — 2013-04-22T09:00:00+09:00

Authors: Sanghoon Lee, Soichiro Kanno, Hisashi Kino, and Tetsu Tanaka
We have fabricated various types of Si neural probe for in vivo and in vitro neuronal signal recordings by combining standard photolithography with a bulk micromachining process. To place the probe tip at target areas in the brain precisely, the mechanical properties of the Si neural probes with various tip shapes were carefully investigated under different insertion conditions to brain phantoms. As results, the minimum length and penetration force of the Si neural probe were determined from conditions where the Si neural probe began to penetrate the surface of the brain phantom. To control buckling of the Si neural probe, it is necessary to optimize the insertion rate in accordance with the conditions of the Si neural probe. Although the insertion forces of the Si neural probe with a sharpened tip were smaller than those of the Si neural probe with a normal tip, the effect of the probe tip shape became small with increased insertion speeds.

A Wearable Capacitive Sensor for Monitoring Human Respiratory Rate

Subrata Kumar Kundu, Shinya Kumagai, and Minoru Sasaki — 2013-04-22T09:00:00+09:00

Authors: Subrata Kumar Kundu, Shinya Kumagai, and Minoru Sasaki
Realizing an untethered, low-cost, and comfortably wearable respiratory rate sensor for long-term breathing monitoring application still remains a challenge. In this paper, a conductive-textile-based wearable respiratory rate sensing technique based on the capacitive sensing approach is proposed. The sensing unit consists of two conductive textile electrodes that can be easily fabricated, laminated, and integrated in garments. Respiration cycle is detected by measuring the capacitance of two electrodes placed on the inner anterior and posterior sides of a T-shirt at either the abdomen or chest position. A convenient wearable respiratory sensor setup with a capacitance-to-voltage converter has been devised. Respiratory rate as well as breathing mode can be accurately identified using the designed sensor. The sensor output provides significant information on respiratory flow. The effectiveness of the proposed system for different breathing patterns has been evaluated by experiments.

Detection of Sub-Nano-Tesla Magnetic Field by Integrated Magnetic Tunnel Junctions with Bottom Synthetic Antiferro-Coupled Free Layer

2013-04-22T09:00:00+09:00

Authors: Kosuke Fujiwara, Mikihiko Oogane, Takuo Nishikawa, Hiroshi Naganuma, and Yasuo Ando
Arrays of 100×100 magnetic tunnel junctions (MTJs) connected in parallel and series were fabricated. A synthetic antiferro-coupled bottom free layer with a NiFe/Ru/CoFeB structure and MgO tunneling barrier were used to realize a high sensitivity, which is defined as TMR/2H_{k}, where, TMR is the tunneling magnetoresistance ratio and H_{k} is the magnetic anisotropy field of the free layer. To obtain a linear response of tunneling resistance against an applied external magnetic field, a double annealing process was carried out. From R–H curve measurements, the sensitivity of the 100×100 integrated MTJs was lower (8%/Oe) than that of a single MTJ (25%/Oe). However, a 1/30 decrease in noise power density was realized in the integrated MTJs. Consequently, a very small magnetic field of 0.29 nT was detected with the integrated MTJs.

Circuit-Level Model of Phase-Locked Spin-Torque Oscillators

Sora Ahn, Hyein Lim, Miryeon Kim, Hyungsoon Shin, and Seungjun Lee — 2013-04-22T09:00:00+09:00

Authors: Sora Ahn, Hyein Lim, Miryeon Kim, Hyungsoon Shin, and Seungjun Lee
Spin-torque oscillators (STOs) are new oscillating devices based on spintronics technology with many advantageous features, i.e., nanoscale size, high tunability, and compatibility with standard silicon processing. Recent research has shown that two electrically connected STOs may operate as a single device when specific conditions are met. To overcome the limitation of the small output power of STOs, the phase-locking behavior of multiple STOs is hereby extensively investigated. In this paper, we present a circuit-level model of two coupled STOs considering the interaction between them such that it can represent the phase-locking behavior of multiple STOs. In our model, the characteristics of each STO are defined first as functions of applied DC current and external magnetic field. Then, the phase-locking condition is examined to determine the properties of the two coupled STOs on the basis of a theoretical model. The analytic model of two coupled STOs is written in Verilog-A hardware description language. The behavior of the proposed model is verified by circuit-level simulation using HSPICE with CMOS circuits including a current-mirror circuit and differential amplifiers. Simulation results with various CMOS circuits have confirmed the effectiveness of our model.

Triggering Mechanism for Neutron Induced Single-Event Burnout in Power Devices

Tomoyuki Shoji, Shuichi Nishida, and Kimimori Hamada — 2013-04-22T09:00:00+09:00

Authors: Tomoyuki Shoji, Shuichi Nishida, and Kimimori Hamada
Cosmic ray neutrons can trigger catastrophic failures in power devices. It has been reported that parasitic transistor action causes single-event burnout (SEB) in power metal–oxide–semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). However, power diodes do not have an inherent parasitic transistor. In this paper, we describe the mechanism triggering SEB in power diodes for the first time using transient device simulation. Initially, generated electron–hole pairs created by incident recoil ions generate transient current, which increases the electron density in the vicinity of the n^{-}/n^{+} boundary. The space charge effect of the carriers leads to an increase in the strength of the electric field at the n^{-}/n^{+} boundary. Finally, the onset of impact ionization at the n^{-}/n^{+} boundary can trigger SEB. Furthermore, this failure is closely related to diode secondary breakdown. It was clarified that the impact ionization at the n^{-}/n^{+} boundary is a key point of the mechanism triggering SEB in power devices.

Compact Modeling of Floating-Base Effect in Injection-Enhanced Insulated-Gate Bipolar Transistor Based on Potential Modification by Accumulated Charge

Takao Yamamoto, Masataka Miyake, and Mitiko Miura-Mattausch — 2013-04-22T09:00:00+09:00

Authors: Takao Yamamoto, Masataka Miyake, and Mitiko Miura-Mattausch
We have developed a compact model of the injection-enhanced insulated-gate bipolar transistor (IGBT) applicable for circuit optimization. The main development is modeling the hole accumulation in the floating-base region. It is demonstrated that the observed negative gate capacitance is well reproduced with the developed model.

Parasitic Bipolar Effect of a Thin-Film Silicon-on-Insulator Power Metal–Oxide–Semiconductor Field-Effect Transistor at High Temperatures

Atsushi Uchida, Yuka Morisawa, and Satoshi Matsumoto — 2013-04-22T09:00:00+09:00

Authors: Atsushi Uchida, Yuka Morisawa, and Satoshi Matsumoto
In this paper, we describe the parasitic bipolar effect of the fabricated thin-film silicon-on-insulator (SOI) power metal–oxide–semiconductor field-effect transistor (MOSFET) at high temperatures. This effect in the on-state was suppressed as temperature increased. This effect in the off-state was promoted as temperature and body contact pitch increased. The parasitic bipolar effect caused by the thermally generated current is enhanced by increasing temperature and decreasing channel length. This reduced breakdown voltage.

Plan-View and Cross-Sectional Photoluminescence Imaging Analyses of Threading Dislocations in 4H-SiC Epilayers

Masahiro Nagano, Isaho Kamata, and Hidekazu Tsuchida — 2013-04-22T09:00:00+09:00

Authors: Masahiro Nagano, Isaho Kamata, and Hidekazu Tsuchida
We performed a plan-view and cross-sectional photoluminescence (PL) imaging and a spectral analysis of threading dislocations in 4H-SiC epilayers in the near-infrared region. The bright PL spots of threading screw dislocations (TSDs) and threading edge dislocations (TEDs) observed in the plan-view PL imaging are compared with the grazing incidence synchrotron X-ray topography contrast, and precise discrimination of threading dislocations using the PL technique and the direct acquisition of Burgers vector directions of TEDs are demonstrated. The inclination angles of TSDs and TEDs across a thick epilayer are revealed by the cross-sectional PL imaging, and the variations in the plan-view PL appearances of the threading dislocations are confirmed to originate from the line directions of such dislocations.

Conductivity Degradation of 4H-SiC p–i–n Diode with In-Grown Stacking Faults

2013-04-22T09:00:00+09:00

Authors: Atsushi Tanaka, Koji Nakayama, Katsunori Asano, Tetsuya Miyazawa, and Hidekazu Tsuchida
The electrical characteristics of 4H-SiC p–i–n diodes with 8H-type in-grown stacking faults are investigated. The 4H-SiC p–i–n diodes have epilayers with a low Z_{1/2} center density formed by carbon implantation. The forward voltage drops of the 4H-SiC p–i–n diode with 8H-type in-grown stacking faults are larger than those of the 4H-SiC p–i–n diode without an 8H-type in-grown stacking fault. The differential on-resistance of the 4H-SiC p–i–n diode with 8H-type in-grown stacking faults is larger than the drift resistance of the drift layer calculated from the doping density and thickness of the drift layer. A large number of electrons are trapped at 8H-type in-grown stacking faults, and the effective carrier density decreases compared with the doping density.

Ion Shower Doping Technique for Selective Emitter Structure in Crystalline Silicon Solar Cells

2013-04-22T09:00:00+09:00

Authors: Hiroki Hashiguchi, Tomihisa Tachibana, Mari Aoki, Takuto Kojima, Yoshio Ohshita, and Atsushi Ogura
For realizing low-cost and high-conversion-efficiency silicon solar cells, we propose an ion shower doping technique for fabricating conventional and selective emitter structure solar cells. Because of its high through put with a large beam area, the technique could lead to low-cost production of the emitter layer. We used this technique to form a uniform emitter layer and also a selective high-doping emitter region for silicon solar cells, which were compared with cells prepared by POCl_{3} diffusion. The conventional structure cells were confirmed to have good electrical properties with uniform conversion efficiency compared with the cells prepared by POCl_{3} diffusion. There was no doping-induced damage nor metal impurities interfused during the ion shower doping. In addition, the conversion efficiency of selective emitter structure cells was higher than that of cell prepared by POCl_{3} diffusion only. We concluded that the ion shower doping technique is useful for forming a uniform emitter layer as well as a selective emitter region.

Spectroscopic Detection of Medium Range Order in Device Grade Hydrogenated Amorphous Silicon

Gerry Lucovsky, Greg Parsons, Daniel Zeller, and Jinwoo Kim — 2013-04-22T09:00:00+09:00

Authors: Gerry Lucovsky, Greg Parsons, Daniel Zeller, and Jinwoo Kim
This article addresses low defect densities in hydrogenated amorphous silicon, a-Si_{1-x}:H_{x} with approximately 10 at. % bonded H, x∼0.1. Based low defect densities at mid-gap, ∼0.5 to 1×10^{16} cm^{-3}, a-Si:H thin films have been integrated into photovoltaic (PV) devices and thin film transistors (TFT's). Amorphous Si (a-Si) thin films with no detectable bonded-H have been used as precursors for polycrystalline gate electrodes in microelectronic applications. PV and TFT alloys have been deposited by glow discharge (GD), remote plasma-enhanced chemical vapor deposition (RPECVD), and reactive magnetron sputtering (RMS) with different bonded-H content determined by deposition precursors and substrate temperatures. Two conditions are required for the lowest Si dangling bond densities: (i) a monohydride, Si–H, concentration of ∼10 at. % H, and (ii) deposition, and/or a post-deposition annealing at 240 to 300 °C.

Defect Termination of Flash-Lamp-Crystallized Large-Grain Polycrystalline Silicon Films by High-Pressure Water Vapor Annealing

Keisuke Ohdaira — 2013-04-22T09:00:00+09:00

Authors: Keisuke Ohdaira
High-pressure water-vapor annealing (HPWVA) is performed on 3-µm-thick polycrystalline silicon (poly-Si) films formed on glass substrates by crystallizing electron-beam (EB)-evaporated precursor amorphous Si (a-Si) films by flash lamp annealing (FLA). HPWVA at higher temperature and pressure tends to result in a lower defect density of FLC poly-Si films. The defect density of FLC poly-Si films can be reduced from ∼3×10^{17} to ∼2×10^{16}/cm^{3} when the HPWVA temperature is 500 °C and the pressure is more than 8 MPa, which is sufficiently of device grade. The annealing of flash-lamp-crystallized (FLC) poly-Si films under inert-gas atmosphere does not lead to sufficient reduction in their defect density, indicating the necessity of water vapor during annealing.

Improvement of Photovoltaic Characteristics by MoO_{3} Doping of Thick Hole-Transporting Films

Yusuke Shinmura, Masayuki Kubo, Toshihiko Kaji, and Masahiro Hiramoto — 2013-04-22T09:00:00+09:00

Authors: Yusuke Shinmura, Masayuki Kubo, Toshihiko Kaji, and Masahiro Hiramoto
Thick heterojunction cells composed of fullerene and p-type hole-transporting materials (HTMs) doped with molybdenum oxide (MoO_{3}) were fabricated. The Fermi level (E_{F}) of HTMs shifted toward the positive direction and close to the upper edge of the valence band following MoO_{3} doping. These E_{F} shifts indicate that intrinsic HTMs changed to be of the p-type. The introduction of p-type HTMs to the cells increased photocurrent density and fill factor. The increase in photocurrent density can be explained by the formation of built-in potential at the interface between p-type HTMs and C_{60}. On the other hand, the increase in fill factor can be explained by the drastic decrease in the resistance of 300-nm-thick HTM films, which reached a very small value of 2 Ω.

Incorporation Effect of Silver Nanoparticles on Inverted Type Bulk-Heterojunction Organic Solar Cells

Taisuke Matsumoto, Takeo Oku, and Tsuyoshi Akiyama — 2013-04-22T09:00:00+09:00

Authors: Taisuke Matsumoto, Takeo Oku, and Tsuyoshi Akiyama
A series of bulk-heterojunction organic solar cells incorporating silver nanoparticles was fabricated and evaluated. Silver nanoparticles were incorporated in the hole-transport layer of the solar cells. Plasmonic absorption and the generation of localized surface plasmon resonance of silver nanoparticles were confirmed by absorption and surface enhanced Raman scattering spectra even in the hole-transport material. The incorporation of silver nanoparticles increased photoelectric conversion efficiencies, whose enhancement properties were varied by the incorporation amount of silver nanoparticles.

Physical Properties of Amorphous In–Ga–Zn–O Films Deposited at Different Sputtering Pressures

2013-03-21T09:00:00+09:00

Authors: Satoshi Yasuno, Takashi Kita, Aya Hino, Shinya Morita, Kazushi Hayashi, and Toshihiro Kugimiya
The physical properties of amorphous In–Ga–Zn–O (a-IGZO) films deposited by DC sputtering under various sputtering pressures were investigated. The sputtering pressure was found to influence various physical properties. Lower sputtering pressures resulted in film densification and decreased both surface roughness and hydrogen concentration. In addition, transistor performance characteristics such as saturation mobility and sub-threshold swing improved as the sputtering pressure decreased. These results yield insight into the correlation between thin film transistor (TFT) performance and deposition conditions.

Fabrication of Zinc Oxide Nanopatterns by Quick Gel-Nanoimprint Process toward Optical Switching Devices

2013-03-21T09:00:00+09:00

Authors: Shinji Araki, Yasuaki Ishikawa, Min Zhang, Takahiro Doe, Li Lu, Masahiro Horita, Takashi Nishida, and Yukiharu Uraoka
We proposed a quick patterning method using a gel-nanoimprint process to fabricate a photonic crystal layer using zinc oxide (ZnO). The X-ray diffraction measurement revealed that the ZnO layer had a wurtzite structure by annealing in air or oxygen ambient. We demonstrated the nanopatterning with a short imprinting time of 5 min by the gel-nanoimprint process. We achieved shrinkage factors of ZnO nanopatterns of as low as 8 and 3% in the width and height directions, respectively. In addition, the uniformity in size of the patterned area was found to be 3% in our process, suggesting that the gel-nanoimprint process allows us to fabricate optical switching devices.

Impact of the Hydrogenation Process on the Performance of Self-Aligned Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors

2013-03-21T09:00:00+09:00

Authors: Yusuke Shika, Takuro Bessho, Yasunori Okabe, Hiroyuki Ogata, Shinya Kamo, Kuninori Kitahara, and Akito Hara
We investigated hydrogenation of low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) from the point of view of the gettering phenomenon, specifically, using self-aligned metal double-gate p-channel LT poly-Si TFTs that had a small subthreshold swing value and a high field-effect mobility. Hydrogenation of TFTs was carried out by forming gas annealing. Our results indicate that the conventionally used hydrogenation temperature of 400 °C is considerably high because annealing at this temperature results in the re-emission of gettered hydrogen. Moreover, when annealing in forming gas, hydrogenation actually occurs during cooling from 400 °C, but not at 400 °C. The most important parameter for effective hydrogenation is the rate of cooling from 400 °C, but not the hydrogenation temperature of 400 °C.

Double-Crystalline Silicon Channel Thin Film Transistors Fabricated Using Continuous-Wave Green Laser for Large Organic Light-Emitting Diode Displays

2013-03-21T09:00:00+09:00

Authors: Hiroshi Hayashi, Arinobu Kanegae, Kenichirou Nishida, Takahiro Kawashima, Tohru Saitoh, and Kazunori Komori
We developed double-crystalline silicon channel thin film transistors (TFTs) whose active region consisted of a polysilicon layer and a microcrystalline silicon layer. The polysilicon layer was formed by continuous-wave green laser annealing with scalability to large substrates. The microcrystalline silicon layer formed on the polysilicon layer provides a sufficient channel etching margin for the fabrication of TFTs on large substrates without degradation of TFT mobility. The kink-free output characteristics were realized by a band-gap engineering method using a microcrystalline silicon layer. The TFT characteristics desirable for organic light-emitting diode display applications, namely, high mobility, high reliability, and kink-free output characteristics, have been successfully demonstrated.

Depth-Profiling Study on Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors by X-ray Photoelectron Spectroscopy

2013-03-21T09:00:00+09:00

Authors: Shinnosuke Iwamatsu, Kazushige Takechi, Toru Yahagi, Yoshiyuki Watanabe, Hiroshi Tanabe, and Seiya Kobayashi
We performed an X-ray photoelectron spectroscopy (XPS) depth-profiling study on the materials used in amorphous indium–gallium–zinc oxide thin-film transistors (a-IGZO TFTs) with Ti and Mo source/drain (S/D) electrodes. The XPS results suggested that there are some differences between the interface regions of Ti/a-IGZO and Mo/a-IGZO for different chemical states of the materials. The chemical states of the back-channel surfaces were also found to be different between the TFTs with Ti and Mo S/D electrodes. In addition, we fabricated indium–gallium–zinc–titanium oxide composite thin films by deposition using multitarget co-sputtering. The electronic structure of these films observed by XPS is similar to that of the Ti/a-IGZO interface region. The fabricated films were found to have a very low resistivity, much lower than that of an a-IGZO film using typical TFT fabrication processes.

Influence of Oxide Semiconductor Thickness on Thin-Film Transistor Characteristics

2013-03-21T09:00:00+09:00

Authors: Mitsuru Nakata, Hiroshi Tsuji, Hiroto Sato, Yoshiki Nakajima, Yoshihide Fujisaki, Tatsuya Takei, Toshihiro Yamamoto, and Hideo Fujikake
We discuss here the influence of oxide semiconductor thickness on thin-film transistor (TFT) characteristics. We have determined this influence by measuring the transfer characteristics of amorphous InGaZnO (IGZO) TFTs having various IGZO thicknesses and using a simple method to calculate the depletion width in IGZO films. ON current was nearly constant with respect to IGZO thickness because it depended on a high electron density in an accumulation region sufficiently thinner than the IGZO film. The threshold voltage shifted negatively with increasing IGZO thickness, which indicates that a thicker IGZO film requires a higher negative gate voltage for it to be fully depleted. Calculation results suggest that threshold voltage variation due to IGZO thickness variation increases with increasing donor density and IGZO thickness.

Scaling of Coplanar Homojunction Amorphous In–Ga–Zn–O Thin-Film Transistors

Gwanghyeon Baek, Katsumi Abe, Hideya Kumomi, and Jerzy Kanicki — 2013-03-21T09:00:00+09:00

Authors: Gwanghyeon Baek, Katsumi Abe, Hideya Kumomi, and Jerzy Kanicki
Channel length (L) and width (W) scaling of amorphous In–Ga–Zn–O (a-IGZO) thin-film transistors (TFTs) have been investigated by coplanar homojunction a-IGZO TFTs. The fabricated TFTs have a mobility around 12 cm^{2} V^{-1} s^{-1}, sub-threshold slope (S) of ∼110 mV/decade, threshold voltage around 0.3 V and off-current below 10^{-13} A. The TFTs with L > 5 µm have the reduced transconducance (g_{m}) at lower V_{GS}, however, the short L < 5 µm TFTs have the g_{m} reduction at higher V_{GS}. Even though the TFTs with smaller channel length (L ≤5 µm) show proper switching characteristics, threshold voltage lowering and sub-threshold slope degradation are clearly observed.

Approaches to Decreasing the Processing Temperature for a Solution-Processed InZnO Thin-Film Transistors

Dong Lim Kim, Woong Hee Jeong, and Hyun Jae Kim — 2013-03-21T09:00:00+09:00

Authors: Dong Lim Kim, Woong Hee Jeong, and Hyun Jae Kim
In this paper, the formation of a dual active layer (DAL) and utilization of a nitrate precursor are proposed to decrease the processing temperature for solution-processed thin-film transistors (TFTs). In the DAL approach, the conductivity decline of a conventional solution-processed AlInZnO (AIZO) was complemented by stacking a highly conductive InZnO (IZO) layer at the bottom of the DAL structure. Further decrease in processing temperature was achieved for the IZO TFT with a zinc nitrate precursor, which showed a weaker decomposition behavior than Zn acetate. Using DAL and the nitrate precursor, TFTs with field-effect mobilities of 2.89 (fabricated at 350 °C) and 0.21 cm^{2} V^{-1} s^{-1} (fabricated at 250 °C) were achieved, respectively.

Phenylene–Thiophene Oligomer Derivatives for Thin-Film Transistors: Structure and Semiconductor Performances

2013-03-21T09:00:00+09:00

Authors: Zongfan Duan, Hirokuni Ohuchi, Yuichiro Yanagi, Yutaro Takayanagi, Gaoyang Zhao, and Yasushiro Nishioka
Two phenylene–thiophene oligomer derivatives, 2,8-bis[5-(4-n-hexylphenyl)-2-thienyl]dibenzothiophene (28HPTDBT) and 3,7-bis[5-(4-n-hexylphenyl)-2-thienyl]dibenzothiophene (37HPTDBT), were used as active materials in thin-film organic field-effect transistors (OFETs). Although the two molecules have similar structures, they exhibited obvious differences in photophysical, crystal, π-stacking, and electrical properties. 28HPTDBT is an amorphous material and hence showed no semiconductor characteristics in its thin-film OFETs, while 37HPTDBT exhibited high crystallinity and strong π-stacking in the solid state, thus resulting in high charge carrier mobilities. The effects of gate insulators and annealing treatment on transistor performances were also investigated. Thin-film OFETs based on 37HPTDBT with an octadecanyltrichlorosilane (OTS)-treated SiO_{2} gate insulator exhibited excellent field-effect performances with a maximum mobility of 0.3 cm^{2} V^{-1} s^{-1} and a high I_{on}/I_{off} current ratio of 1.5×10^{5}. Although annealing treatment improved the crystallinity of the thin films, the appearance of voids (cracks) resulted in a decrease in the charge carrier mobilities in the OFETs.

Performance Enhancement of Top-Contact Pentacene-Based Organic Thin-Film Transistors with Bilayer WO_{3}/Au Electrodes

Mir Waqas Alam, Zhaokui Wang, Shigeki Naka, and Hiroyuki Okada — 2013-03-21T09:00:00+09:00

Authors: Mir Waqas Alam, Zhaokui Wang, Shigeki Naka, and Hiroyuki Okada
We fabricated top-contact pentacene-based organic thin-film transistors (OTFTs) with bilayer WO_{3}/Au electrodes. Compared with those of a device without a WO_{3} layer, the performance characteristics including field-effect mobility, threshold voltage, and On/Off ratio were highly improved in a device with a 5 nm WO_{3} hole injection layer inserted. The field-effect mobility was increased from 0.47 to 0.69 cm^{2} V^{-1} s^{-1} and the On/Off ratio was also increased from 1.8×10^{4} to 4.1×10^{4}. From the results of evaluating the temperature dependence of I_{D}–V_{D} characteristics and the surface morphology of pentacene, the improved device performance was attributed to reductions in barrier height and surface roughness after inserting a suitable WO_{3} layer between the pentacene and gold electrodes.

Thin-Film Transistors Using Uniform and Well-Aligned Single-Walled Carbon Nanotubes Channels by Dielectrophoretic Assembly

Tatsuya Toda, Hiroshi Frusawa, and Mamoru Furuta — 2013-03-21T09:00:00+09:00

Authors: Tatsuya Toda, Hiroshi Frusawa, and Mamoru Furuta
A single-walled carbon nanotube thin-film transistor (SWCNT TFT) was formed by an aligned SWCNTs channel assembled by the dielectrophoretic (DEP) process. In this work, we investigated the effects of the DEP factors (frequency, solution concentration) on structural (orientation and density in the SWCNT channels) and electrical properties of SWCNT TFTs. A uniform, well-aligned and density controlled SWCNT channel was achieved by optimizing the DEP assembly process, and as a result, electrical properties (mobility and on/off current ratio) of SWCNT TFTs were improved. In addition, we also discussed the effect of uniformity of assembled SWNTs in a channel on performance variation of the SWCNT TFTs. We found that the tube density and uniformity are key parameters which determine electrical properties and performance variation of SWCNT TFTs.

Compact Decoder-Type Gate Driver Circuits with Hydrogenated Amorphous Silicon Thin Film Transistors for Active Matrix Displays

Jong-Seok Kim, Gyu-Tae Park, Hyun-Woo Kim, and Byong-Deok Choi — 2013-03-21T09:00:00+09:00

Authors: Jong-Seok Kim, Gyu-Tae Park, Hyun-Woo Kim, and Byong-Deok Choi
In this paper, we propose an integrated hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) gate driver circuit with parallely connected TFTs to resolve problems of the large circuit area and large number of input signals which are founded in the previously reported decoder-type and demultiplexer-type integrated gate drivers. The proposed gate driver can alleviate the demerits of previous gate drivers while maintaining their advantages: reduction of the threshold voltage (V_{th}) shift of the a-Si:H TFTs with an AC-driving structure and provide a stable low-impedance output. The key idea is to construct a novel decoder based on parallely connected TFTs instead of serially connected ones that are very common for decoders. The simulation results show that the rising time and falling time are 1.27 and 1.63 µs respectively with -5 to 30 V output voltage swing which are suitable for high resolution active-matrix displays.

Fabrication and Characterization of Flexible Organic Light Emitting Diodes Based on Transparent Flexible Clay Substrates

2013-03-21T09:00:00+09:00

Authors: Shanmugam Venkatachalam, Hiromichi Hayashi, Takeo Ebina, Takashi Nakamura, and Hiroshi Nanjo
In the present work, transparent flexible polymer-doped clay (P-clay) substrates were prepared for flexible organic light emitting diode (OLED) applications. Nanocrystalline indium tin oxide (ITO) thin films were prepared on P-clay substrates by ion-beam sputter deposition method. The structural, optical, and electrical properties of as-prepared ITO/P-clay showed that the as-prepared ITO thin film was amorphous, and the average optical transparency and sheet resistance were around 84% and 56 Ω/\square, respectively. The as-prepared ITO/P-clay samples were annealed at 200 and 270 °C for 1 h to improve the optical transparency and electrical conductivity. The average optical transparency was found to be maximum at an annealing temperature of 200 °C. Finally, N,N-bis[(1-naphthyl)-N,N '-diphenyl]-1,1'-biphenyl)-4,4'-diamine (NPB), tris(8-hydroxyquinoline) aluminum (Alq3) thin films, and aluminum (Al) electrode were prepared on ITO/P-clay substrates by thermal evaporation method. The current density–voltage (J–V) characteristic of Al/NPB/ITO/P-clay showed linear Ohmic behaviour. In contrast, J–V characteristic of Al/Alq3/NPB/ITO/P-clay showed non-linear Schottky behaviour. Finally, a very flexible OLED was successfully fabricated on newly fabricated transparent flexible P-clay substrates. The electroluminescence study showed that the emission intensity of light from the flexible OLED device gradually increased with increasing applied voltage.

Highly Conductive Flexible Multi-Walled Carbon Nanotube Sheet Films for Transparent Touch Screen

Daewoong Jung, Kyung H. Lee, Dorothea Burk, Lawrence J. Overzet, and Gil S. Lee — 2013-03-21T09:00:00+09:00

Authors: Daewoong Jung, Kyung H. Lee, Dorothea Burk, Lawrence J. Overzet, and Gil S. Lee
Highly conductive and transparent thin films were prepared using highly purified multi-walled carbon nanotube (MWCNT) sheets. The electrical properties of the MWCNT sheet were remarkably improved by an acid treatment, resulting in densely packed MWCNTs. The morphology of the sheets reveals that continuous electrical pathways were formed by the acid treatment, greatly improving the sheet resistance all the while maintaining an excellent optical transmittance. These results encourage the use of these MWCNT sheets with low sheet resistance (450 Ω/sq) and high optical transmittance (90%) as a potential candidate for flexible display applications.

Reactive Ion Etching Texturing for Multicrystalline Silicon Solar Cells Using a SF_{6}/O_{2}/Cl_{2} Gas Mixture

Kwang Mook Park, Myoung Bok Lee, Kyeong Su Jeon, and Sie Young Choi — 2013-03-21T09:00:00+09:00

Authors: Kwang Mook Park, Myoung Bok Lee, Kyeong Su Jeon, and Sie Young Choi
Maskless random reactive ion etching (RIE) texturing employing a SF_{6}/O_{2}/Cl_{2} gas mixture was investigated in order to achieve higher efficiencies in multicrystalline silicon (mc-Si) solar cells. Triangular pyramid structures with an aspect ratio of 1 were formed and, when the RIE power increased, the average reflectance was reduced by about 1.46% per 10 W. This was due to the increased density of the surface features. The performances of all of the RIE-textured mc-Si solar cells were improved compared with that of the reference cell. Among them, the 110 W cell, which had a 0.6% higher efficiency than the reference cell, had the highest efficiency of 16.82%. An impedance analysis was carried out to determine series resistance (R_{s}), shunt resistance (R_{sh}), and junction capacitance (C_{j}). Interestingly, the cell with higher efficiencies and higher structure densities had higher linear reverse currents.

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

2013-03-21T09:00:00+09:00

Authors: Anabela Veloso, Soon Aik Chew, Yuichi Higuchi, Lars-Åke Ragnarsson, Eddy Simoen, Tom Schram, Thomas Witters, Annemie Van Ammel, Harold Dekkers, Hilde Tielens, Katia Devriendt, Nancy Heylen, Farid Sebaai, Stephan Brus, Paola Favia, Jef Geypen, Hugo Bender, Anup Phatak, Michael S. Chen, Xinliang Lu, Seshadri Ganguli, Yu Lei, Wei Tang, Xinyu Fu, Srinivas Gandikota, Atif Noori, Adam Brand, Naomi Yoshida, Aaron Thean, and Naoto Horiguchi
This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (V_{T}) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (J_{G}). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-V_{T}: 1) conformal, lower-J_{G} ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes

2013-03-21T09:00:00+09:00

Authors: Anabela Veloso, Soon Aik Chew, Tom Schram, Harold Dekkers, Annemie Van Ammel, Thomas Witters, Hilde Tielens, Nancy Heylen, Katia Devriendt, Farid Sebaai, Stephan Brus, Lars-Åke Ragnarsson, Luigi Pantisano, Geert Eneman, Laure Carbonell, Olivier Richard, Paola Favia, Jef Geypen, Hugo Bender, Yuichi Higuchi, Anup Phatak, Aaron Thean, and Naoto Horiguchi
In this work we provide a comprehensive evaluation of a novel, low-resistance Co–Al alloy vs W to fill aggressively scaled gates with high aspect-ratios [gate height (H_{gate}) ∼50–60 nm, gate length (L_{gate}) ≥20–25 nm]. We demonstrate that, with careful liner/barrier materials selection and tuning, well-behaved devices are obtained, showing: tight gate resistance (R_{gate}) distributions down to L_{gate}∼20 nm, low threshold voltage (V_{T}) values, comparable DC and bias temperature instability (BTI) behavior, and improved RF response. The impact of fill-metals intrinsic stress, including the presence of occasional voids in narrow W-gates, on devices fabrication and performance is also explored.

Quantitative Evaluation of Dopant Concentration in Shallow Silicon p–n Junctions by Tunneling Current Mapping with Multimode Scanning Probe Microscopy

2013-03-21T09:00:00+09:00

Authors: Leonid Bolotov, Koichi Fukuda, Hiroshi Arimoto, Tetsuya Tada, and Toshihiko Kanayama
Quantitative evaluation of the dopant concentration across silicon p–n junctions has been performed on oxide-passivated surfaces by using tunneling current mapping in the constant-gap mode of a multimode scanning probe microscope (MSPM). A distinct difference between regions with different impurity concentrations was observed in tunneling current maps when a constant tunneling gap was maintained by using repulsive force acting on the MSPM probe. To extract impurity profiles, the results of three-dimensional device simulations within the current continuity model were compared with measured bias-dependent current profiles. The obtained impurity profiles showed agreement with the actual donor concentration in the p–n junction region. The results demonstrate the applicability of the method for quantitative analysis of the local impurity distribution in modern semiconductor devices with improved sensitivity and nanometer spatial resolution.

Measurement of Anisotropic Biaxial Stresses in Si_{1-x}Ge_{x}/Si Mesa Structures by Oil-Immersion Raman Spectroscopy

Daisuke Kosemura, Motohiro Tomita, Koji Usuda, Tsutomu Tezuka, and Atsushi Ogura — 2013-03-21T09:00:00+09:00

Authors: Daisuke Kosemura, Motohiro Tomita, Koji Usuda, Tsutomu Tezuka, and Atsushi Ogura
Anisotropic biaxial stress states in Si_{1-x}Ge_{x}/Si mesa structures were evaluated by oil-immersion Raman spectroscopy. Using a high-numerical-aperture lens, the electrical field component perpendicular to the surface, i.e., z-polarization, can be obtained. The z-polarization enables the excitation of the forbidden optical phonon mode, i.e., the transverse optical (TO) phonon mode, even under the backscattering geometry from (001)-oriented diamond-type crystals. The anisotropic biaxial stress evaluation of Si_{1-x}Ge_{x} was considered difficult compared with that of Si, because many unknown parameters exist for Si_{1-x}Ge_{x}, e.g., phonon deformation potentials (PDPs), the Ge concentration x, and the factor of Raman shift on x. In this study, PDPs and the Ge concentration in Si_{1-x}Ge_{x} were investigated in detail. As a result, using precise PDPs and x, a clear dependence of anisotropic biaxial stress states in Si_{1-x}Ge_{x} on the mesa structure shape was observed.

Tensor Evaluation of Anisotropic Stress Relaxation in Mesa-Shaped SiGe Layer on Si Substrate by Electron Back-Scattering Pattern Measurement: Comparison between Raman Measurement and Finite Element Method Simulation

2013-03-21T09:00:00+09:00

Authors: Motohiro Tomita, Masaya Nagasaka, Daisuke Kosemura, Koji Usuda, Tsutomu Tezuka, and Atsushi Ogura
A strained SiGe layer will be used in next-generation transistors to improve device performance along with device scaling. However, the stress relaxation of the SiGe layer may be inevitable in nanodevices, because the SiGe layer is processed into a nanostructure. In this study, we evaluated the anisotropic stress relaxation in mesa-shaped strained SiGe layers on a Si substrate by electron backscattering pattern (EBSP) measurement. Moreover, we compared the results of EBSP measurement with those of anisotropic Raman measurement and finite element method (FEM) simulation. As a result, the anisotropic stress relaxation obtained by Raman spectroscopy was confirmed by EBSP measurement. Additionally, we obtained a good correlation between the results of EBSP measurement and FEM simulation. The σ_{xx} and σ_{yy} stresses were markedly relaxed and the σ_{zz} and σ_{xz} stresses were concentrated at the SiGe layer edges. These stresses were mostly relaxed in the distance range from the SiGe layer edges to 200 nm. Therefore, in a SiGe nanostructure with a scale of less than 200 nm, stress relaxation is inevitable. The results of EBSP and Raman measurements, and FEM simulation show a common tendency. We believe that EBSP measurement is useful for the evaluation of stress tensors and is complementary to Raman measurement.

Towards the Integration of Carbon Nanotubes as Vias in Monolithic Three-Dimensional Integrated Circuits

2013-03-21T09:00:00+09:00

Authors: Sten Vollebregt, Ann N. Chiaramonti, Johan van der Cingel, Kees Beenakker, and Ryoichi Ishihara
Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects (vias) in three-dimensional integrated circuits due to their excellent thermal and electrical properties. To investigate the electrical resistivity of CNT, test vias were fabricated using both a top-down and bottom-up approach. The measured resistivity for the top-down process of 10 mΩ cm is among the better values found in literature. Beside this, the ability to grow CNT directly on single-grain thin-film transistors (SG-TFT) was demonstrated. The electrical performance of the SG-TFT was found not to be influenced by the CNT growth.

Radio-Frequency Inductors on High-Resistivity Silicon Substrates with a Nanocrystalline Silicon Passivation Layer

2013-03-21T09:00:00+09:00

Authors: Ruey-Lue Wang, Chao-Jung Chen, Yu-Ru Lin, Pin-Yi Liu, Yan-Kuin Su, and Ting-Jen Hsueh
In this paper, spiral inductors on high-resistivity silicon (HR-Si) substrates, which surfaces were passivated by different process methods, were fabricated and measured. The comparison of inductances and quality factors between these inductors shows that the inductances and quality factors of spiral inductors significantly depend on process method and thickness of surface passivation layer. The differently generated passivation layer results in different effective substrate resistivity and hence gives rise to different substrate loss. The experimental results show that using thicker nanocrystalline silicon (nc-Si) as a passivation layer will result in a smaller substrate loss and hence spiral inductors on the substrate have larger inductances and larger quality factors. In this study, the metal thickness of inductors is 1.2 µm and is about half that of the inductors provided by foundries. At higher frequencies, the thinner spiral inductors on the SiO_{2}/nc-Si/HR-Si substrate have larger inductances and larger quality factors as compared with the inductors provided by foundries. With the same metal thickness as that adopted in standard processes of foundries, the identical-geometry inductors on the SiO_{2}/nc-Si/HR-Si substrate probably exhibit superior quality factors.

Direct Measurement of Carrier Mobility in Intrinsic Channel Tri-Gate Single Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors

Ke Mao, Takuya Saraya, and Toshiro Hiramoto — 2013-03-21T09:00:00+09:00

Authors: Ke Mao, Takuya Saraya, and Toshiro Hiramoto
In this paper, we report the direct measurement of intrinsic carrier mobility in “single”-silicon-nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) for the first time. To obtain intrinsic carrier mobility with high accuracy by the split capacitance–voltage (C–V) method, ultralong single-silicon-nanowires, instead of multiple parallel nanowires, were designed and fabricated. The open-circuit method was utilized to remove the parasitic effect in measured capacitance. It is found that, although mobility degradations in narrower nanowires are seen in both electrons and holes, the hole mobility is higher than the universal mobility on the (100) surface even in a “single”-nanowire thanks to the high hole mobility on the (110)-oriented side surface of the [110]-directed nanowire. The extracted mobility indicates that surface orientation plays a key role in nanowire mobility.

Impact of Junction Nonabruptness on Random-Discrete-Dopant Induced Variability in Intrinsic Channel Trigate Metal–Oxide–Semiconductor Field-Effect Transistors

Kang Liang Wei, Xiao Yan Liu, and Gang Du — 2013-03-21T09:00:00+09:00

Authors: Kang Liang Wei, Xiao Yan Liu, and Gang Du
Using full three-dimensional (3D) technology computer-aided design (TCAD) simulations, we present a comprehensive statistical study on the random discrete dopant (RDD) induced variability in state-of-the-art intrinsic channel trigate MOSFETs. This paper is focused on the RDD variability sources that are introduced by dopant diffusion from highly doped source/drain (S/D) regions into the undoped channel region, which is referred to as junction nonabruptness (JNA). By considering a realistic lateral doping profile in the channel and evaluating the impact of JNA on the variability of performance parameters such as threshold voltage (V_{th}), subthreshold slope (SS), drain-induced barrier lowering (DIBL), on current (I_{on}), and off current (I_{off}), we show that the effect of JNA can lead to substantial device variations. The nonnegligible influence of JNA puts limitations on device scaling, which is also investigated in this paper.

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

2013-03-21T09:00:00+09:00

Authors: Anabela Veloso, An De Keersgieter, Marc Aoulaiche, Malgorzata Jurczak, Aaron Thean, and Naoto Horiguchi
In this work we explore the use of extension-less doping schemes for fully-depleted devices [two-dimensional (2D): ultra-thin body and buried-oxide layer (BOX) planar devices (UTBB); three-dimensional (3D): multi-gate field-effect transistor devices with the conduction channels wrapped around silicon (Si) fins (FinFETs) and built on bulk-Si or silicon-on-insulator (SOI) substrates], suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised source (S)/drain (D) (SEG) followed by highly doped drain (HDD)-only implantations (I/I), or by using doped-SEG and no I/I: 1) lower off-state current (I_{OFF}) and drain induced barrier lowering effect (DIBL); 2) steeper sub-threshold slope (SS); 3) higher on-state/off-state currents ratio (I_{ON}/I_{OFF}); and 4) higher retention times [for floating body random-access memory (FBRAM) on UTBB] can be obtained, while reducing cost and cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre-clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed.

Effects of Side Surface Roughness on Carrier Mobility in Tri-Gate Single Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors

Ke Mao, Takuya Saraya, and Toshiro Hiramoto — 2013-03-21T09:00:00+09:00

Authors: Ke Mao, Takuya Saraya, and Toshiro Hiramoto
In this paper, the effects of side surface roughness on mobility behaviors in single-silicon-nanowire metal–oxide–semiconductor field-effect transistors (MOSFETs) are discussed on the basis of intrinsic carrier mobility data obtained by direct split capacitance–voltage (C–V) method measurement for the first time. To investigate the mechanisms that dominate the mobility degradation in narrower nanowires, low-temperature measurements are performed. It is found that phonon scattering has little dependence on nanowire width, indicating that the mobility degradation in our tri-gate nanowire MOSFETs is caused by surface roughness scattering. It is also found by analyzing the nanowire width dependence of mobility that the process-induced roughness on the side surface is the main source of mobility degradation in nanowire pFETs, while the degradation caused by the side surface roughness is negligible in nanowire nFETs.

Impact of Deformation Potential Increase at Si/SiO_{2} Interfaces on Stress-Induced Electron Mobility Enhancement in Metal–Oxide–Semiconductor Field-Effect Transistors

Teruyuki Ohashi, Shunri Oda, and Ken Uchida — 2013-03-21T09:00:00+09:00

Authors: Teruyuki Ohashi, Shunri Oda, and Ken Uchida
The impact of deformation potential increase at metal–oxide–semiconductor (MOS) interfaces on stress effects is thoroughly studied. In our previous study, we revealed that the deformation potential (D_{ac}) of Si increases at MOS interfaces. The energy split between two- and four-fold valleys is proportional to D_{ac}. Therefore, it is considered that the D_{ac} increase at MOS interfaces has an affect on strain effects. D_{ac} effectively changes by adjusting Si-on-insulator (SOI) thickness and carrier distribution at MOS interfaces. Therefore, the SOI thickness dependence and carrier distribution dependence of electron mobility enhancement ratio (Δµ_{e}/µ_{e}) under strain are investigated. Experimental results are explained by the model including the D_{ac} increase at MOS interfaces. In addition, experimental data are well reproduced by calculation using the position-dependent-D_{ac} model. By applying uniaxial strain, effective mass, subband occupation, and intervalley scattering rate are also changed. Their effects on Δµ_{e}/µ_{e} are also discussed in this paper.

Experimental Study on Surface-Orientation/Strain Dependence of Phonon Confinement Effects and Band Structure Modulation in Two-Dimensional Si Layers

2013-03-21T09:00:00+09:00

Authors: Tomohisa Mizuno, Takashi Aoki, Yuhsuke Nagata, Yuhta Nakahara, and Toshiyuki Sameshima
We have experimentally studied the surface orientation/strain effects on quantum mechanical confinement (QMC) in two-dimensional (2D) Si layers with thicknesses less than the Si lattice constant for future metal–oxide–semiconductor (MOS) devices. By UV–Raman spectroscopy, we have demonstrated that the quantum phonon confinement effects (PCEs) rapidly increase with decreasing 2D Si thickness T_{S}, but is almost independent of surface orientation and strain. Thus, electron saturation velocity of the 2D Si is degraded by the reduced phonon energy owing to the PCEs. On the other hand, photoluminescence (PL) emitted from the only (100)-surface 2D Si layers, depends on the excitation photon energy hν (2.33≤hν≤3.81 eV), and PL intensity increases with decreasing T_{S}. The PL data can be explained by simple PL models considering the electron/hole pair recombination mechanism. Consequently, it is necessary to reconstruct the device design for future Si devices, considering the T_{S} dependence of the 2D Si properties.

Novel Extraction Method for Source and Drain Series Resistances in Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect-Transistors Based on Radio-Frequency Analysis

Kyung Rok Kim, Sunhae Shin, Seongjae Cho, Jung-Hee Lee, and In Man Kang — 2013-03-21T09:00:00+09:00

Authors: Kyung Rok Kim, Sunhae Shin, Seongjae Cho, Jung-Hee Lee, and In Man Kang
In this work, we present a novel analytical method based on radio-frequency (RF) analysis for the accurate and reliable extraction of source and drain (S/D) series resistances in silicon nanowire (SNW) metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed method provides decomposed RF model equations for the gate-bias-independent off-state and gate-bias-dependent on-state components from both Y- and Z-parameters. The validity of our extraction method for S/D series resistances in SNW MOSFETs has been carefully tested in comparison with that of a previously reported method as well as with the physical three-dimensional (3D) device simulation. The schematically modeled Y- and Z-parameters have demonstrated excellent agreement with the numerical 3D device simulation results for various SNW MOSFET structures up to the 100 GHz frequency regime.

Impact of Parasitic Bipolar Effect on Single-Event Upset in p-Type Metal–Oxide–Semiconductor Field Effect Transistor with Embedded SiGe

2013-03-21T09:00:00+09:00

Authors: Takashi Kato, Taiki Uemura, Hiroko Mori, Yoshihiro Ikeda, Kaina Suzuki, Shigeo Satoh, and Hideya Matsuyama
Accelerated neutron tests for soft error rate (SER) are carried out using unbalanced feedback-loop circuits fabricated by Si and embedded SiGe (eSiGe) processes. The contribution of the p-type metal–oxide–semiconductor field effect transistor (PMOS) to total SER is shown to substantially decrease in the eSiGe process. The characteristics of parasitic bipolar transistors in PMOSs with and without eSiGe are investigated using technology computer-aided design (TCAD) simulations. We find that the narrow band gap of SiGe causes an increase in the rate of electron flow from the well region (Si) to the source region (SiGe), leading to a decrease in the current gain of the parasitic bipolar transistor in PMOS with eSiGe. Our results indicate that eSiGe can be attributed to the suppression of the parasitic bipolar effect, resulting in a reduced contribution of PMOS to SER.

A Novel Sub-20 V Contact Gate Metal Oxide Semiconductor Field Effect Transistor with Fully Complementary Metal Oxide Semiconductor Compatible Process

Te Liang Lee, Ming Tsang Tsai, Ya Chin King, and Chrong Jung Lin — 2013-03-21T09:00:00+09:00

Authors: Te Liang Lee, Ming Tsang Tsai, Ya Chin King, and Chrong Jung Lin
In this paper, a novel sub-20 V device which is called contact gate MOSFET (CGMOS) with fully CMOS logic compatible process is proposed and demonstrated. Comparing with lateral double diffusion MOSFET (LDMOS), CGMOS uses P substrate instead of N minus layer as drift region in logic process, and a contact on resistance protection oxide (RPO) layers to form an extra gate on the drain side of the channel region to provide a better gate control and reduce the surface field. This new device significantly rises up the breakdown voltage to 18 V with specific on-resistance 8.8 mΩ·mm^{2} in a small high voltage (HV) MOSFET area. Since there is no extra mask for creating the drift region or additional step for the wire bonding, CGMOS makes the integration of high voltage and logic circuits much simpler and area-saving.

An Improved Compact Model for Doped Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors Using a Rigorous Perturbation Method and Higher-Order Correction

Xixiang Feng, Weiling Kang, Qi Cheng, and Yijian Chen — 2013-03-21T09:00:00+09:00

Authors: Xixiang Feng, Weiling Kang, Qi Cheng, and Yijian Chen
An analytic current–voltage (I–V) model for doped double-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) is derived by using a rigorous perturbation method to solve one-dimensional (1D) Poisson's equation. More accurate prediction of the surface potential and I–V characteristics is achieved by introducing a higher-order correction and setting the operating point of Taylor expansion at the channel surface where the major population of mobile charge is located. Both technology computer-aided design (TCAD) simulations and the numerical solution to 1D Poisson's equation verify the improved accuracy of our model compared with Berkeley short-channel insulated-gate FET model (BSIM) model, especially when the gate voltage and doping level are higher. We also discuss and compare the numerical errors caused by the approximations made in BSIM and our models.

A New Methodology for Probing the Electrical Properties of Heavily Phosphorous-Doped Polycrystalline Silicon Nanowires

Horng-Chih Lin, Zer-Ming Lin, and Tiao-Yuan Huang — 2013-03-21T09:00:00+09:00

Authors: Horng-Chih Lin, Zer-Ming Lin, and Tiao-Yuan Huang
In this study, we proposed a new methodology for probing the electrical properties of heavily doped polycrystalline silicon (poly-Si) nanowires (NWs), including active doping concentration, mobility, and interface fixed charge density. Implementation of this procedure is based on the modulation of the device operation of a gate-all-around (GAA) junctionless (J-less) transistor from the gated resistor mode to the ungated one. The extracted carrier concentration in the NW is found to be much lower than that of Hall measurements, while a negative fixed charge density is identified with the procedure. Dopant segregation at the oxide interface is postulated to be closely related to these observations.

Performance Fluctuations in 10-nm Trigate Metal–Oxide–Semiconductor Field-Effect Transistors: Impact of the Channel Geometry

Ralf Granzner, Frank Schwierz, Sonja Engert, and Hannes Töpfer — 2013-03-21T09:00:00+09:00

Authors: Ralf Granzner, Frank Schwierz, Sonja Engert, and Hannes Töpfer
Off-current and threshold voltage fluctuations in trigate (TG), and single-gate (SG) silicon-on-insulator (SOI) MOSFETs with a gate length of 10 nm are studied by means of three-dimensional (3D) device simulations. Special emphasis is paid to the role of the channel design. We demonstrate that both geometry fluctuations and the presence of single charged impurities in the active device regions can easily alter the off-currents of SG and TG MOSFET designs that nominally meet the I_{on}/I_{off} requirements by more than one order of magnitude. It will be shown that regarding the robustness against geometry fluctuations, neither the SG MOSFET nor one of the possible TG MOSFET designs can be preferred in general. The SG concept, however, turns out to be exceptionally robust against threshold voltage fluctuations caused by single charged impurities.

Optimization of Dislocation Edge Stress Effects for Si N-Type Metal–Oxide–Semiconductor Field-Effect Transistors

2013-03-21T09:00:00+09:00

Authors: Ming-Han Liao, Ci-Hua Chen, Li-Chen Chang, Chen Yang, Ming-Yuan Yu, Gan-Han Liu, and Si-Cha Kao
The comprehensive investigation on the effect of dislocation edge stress for Si N-type metal–oxide–semiconductor field-effect transistors (N-MOSFETs) is presented in this work by the experimental measurement and proposed simulation model. The accurate stress measurement in Si oxide dimension (OD) region with and without dislocation edge stress treatment is extracted by atomic force microscope (AFM)–Raman technique with the nanometer level space resolution. Less compressive stress in Si OD region on the real transistor with dislocation edge stress treatment is observed successfully and has its corresponding higher electron carrier mobility, agreed with the strained Si theory. Main reasons for the less compressive stress in the device with dislocation edge stress treatment are the more stress relaxation of the shallow trench insulator (STI) intrinsic compressive stress in modern CMOS process and one layer Si atom missing near the source and drain region along the dislocation line. The measured stress from AFM–Raman spectra experimentally, the simulated stress from proposed finite element method, and its corresponding electrical characteristics agrees well with each other in this work. After the comprehensive understanding and calibrated model for the dislocation edge stress, the relationship between channel stress and dislocation edge shapes, including the angle and length of dislocation lines, is simulated and investigated clearly. It can be found that longer dislocation line and smaller dislocation angle can relax the intrinsic STI compressive stress more and should have the better electron carrier mobility and device performance for N-MOSFETs.

Improved Degradation and Recovery Characteristics of SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors under Negative-Bias Temperature Stress

2013-03-21T09:00:00+09:00

Authors: Do-Young Choi, Chang-Woo Sohn, Hyun Chul Sagong, Eui-Young Jung, Chang Yong Kang, Jeong-Soo Lee, and Yoon-Ha Jeong
This paper describes the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress. The threshold voltage instability (ΔV_{th}) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under real operating conditions, most of the ΔV_{th} caused by hole trapping would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of V_{th}. The SiGe pMOSFETs show lower stress-induced interface traps; thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions.

Effect of Annealing Process on Trap Properties in High-k/Metal Gate n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors through Low-Frequency Noise and Random Telegraph Noise Characterization

2013-03-21T09:00:00+09:00

Authors: Hsu Feng Chiu, San Lein Wu, Yee Shyi Chang, Shoou Jinn Chang, Po Chin Huang, Jone Fang Chen, Shih Chang Tsai, Chien Ming Lai, Chia Wei Hsu, and Osbert Cheng
In this research, trap properties in n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with different annealing sequences have been studied on the basis of low-frequency (1/f) noise and random telegraph noise (RTN) analyses. The 1/f noise results indicate that the source of the drain current fluctuation is electron trapping. The higher trap density in the devices annealed before the TaN layer causes serious noise and lower trap energy in RTN results. The substitution mechanism explains that the increment of defects is due to the additional nitrogen atoms in HfO_{2}. On the contrary, fewer defects in the devices annealed after the TaN layer are due to the effect of passivation in the TiN layer. The defect in HfO_{2} is the source of trapping/detrapping; thus, fewer defects cause the decrement of the fluctuation and the increment of the drain current. We believe that this process has a potential to remove defects in advanced MOSFETs.

1/f Noise Characteristics of Fin-Type Field-Effect Transistors in Saturation Region

2013-03-21T09:00:00+09:00

Authors: Hideo Sakai, Shin-ichi O’uchi, Kazuhiko Endo, Takashi Matsukawa, Yongxun Liu, Yuki Ishikawa, Junichi Tsukada, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Meishoku Masahara, and Hiroki Ishikuro
In this work, we measured 1/f noise of independent-double-gate- (IDG-) fin-type FET (FinFET) which has two independent gates. Flicker noise of common-double-gate- (CDG-) mode which both gates are applied with the same voltage and IDG-mode that has one gate voltage grounded and the other gate voltage applied with arbitrary voltage, and both result were compared with the same drain current (I_{d}). First, we measured relationship between characteristic of the normalized 1/f noise by I_{d} (S_{I_d}/I_{d}^{2}) and characteristic of I_{d}. Both the S_{I_d}/I_{d}^{2} of IDG- and CDG-modes show nearly equal values and tendency. Next, this work also shows the relationship between 1/f noise and vertical electric field (E_{⊥}) of surface of gate oxide film. As a result we could not definitely see a large margin of 1/f noise between CDG- and IDG-modes from E_{⊥}. This work also discovered that 1/f noise was greatly influenced by I_{d} density.

Characterization of Oxide Traps in 28 nm n-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Different Uniaxial Tensile Stresses Utilizing Random Telegraph Noise

2013-03-21T09:00:00+09:00

Authors: Bo-Chin Wang, San-Lein Wu, Yu-Ying Lu, Chien-Wei Huang, Chung-Yi Wu, Yu-Min Lin, Kun-Hsien Lee, Osbert Cheng, Po-Chin Huang, and Shoou-Jinn Chang
In this study, the effect of uniaxial tensile on the SiO_{2}/Si interface of the 28 nm n-type metal–oxide–semiconductor field-effect transistors (nMOSFETs) has been investigated. nMOSFETs were fabricated with different thicknesses of the stress-memorization technique (SMT) films to further increase channel stress because the SMT films can provide a higher uniaxial tensile to the channel. Trap behaviors such as activation energy and depth were characterized on the basis of drain current random telegraph noise (RTN). By RTN analyses, we found that the trap energy level is closer to the channel conduction band as the tensile strain in the channel increases higher, resulting in the trap being located close to the SiO_{2}/Si interface.

Optimization of Conductive Filament of Oxide-Based Resistive-Switching Random Access Memory for Low Operation Current by Stochastic Simulation

2013-03-21T09:00:00+09:00

Authors: Peng Huang, Yexin Deng, Bin Gao, Bing Chen, Feifei Zhang, Di Yu, Lingfeng Liu, Gang Du, Jinfeng Kang, and Xiaoyan Liu
Large switching current is a great challenge for scaling down of the oxide-based resistive random access memory devices to realize high density and low power memory array. In this paper, large operation current caused by the current overshoot effect during forming process is investigated using a stochastic simulator based on the percolation theory. The electrical characteristic of forming process is simulated and compared with the experimental data. Our simulation demonstrates that the current overshoot effect results in a stronger conductive filament during forming process, which will cause a larger operation current in subsequent switching cycle. Furthermore, our simulation results reveal that low sweeping rate, high ambient temperature, high doping concentration and high pre-exist oxygen vacancies (V_{O}) concentration are beneficial to the control of conductive filament evolution and the suppression of the current overshoot effect, which is critical for low reset current and low operation power resistive-switching random access memory (RRAM).

Low Power and Improved Switching Properties of Selector-Less Ta_{2}O_{5} Based Resistive Random Access Memory Using Ti-Rich TiN Electrode

2013-03-21T09:00:00+09:00

Authors: Beomyong Kim, Wangee Kim, Hyojune Kim, Kyooho Jung, Wooyoung Park, Bomin Seo, Moonsig Joo, Keejeung Lee, Kwon Hong, and Sungki Park
The effects of TiN top electrode composition (TiN vs Ti-rich TiN) on the resistive switching characteristics of selector-less TiN/TiO_{x}/Ta_{2}O_{5}/TiN resistive random access memory (ReRAM) are investigated. Ti-rich TiN enables TiO_{x} to have a higher concentration of oxygen vacancy and reduce barrier height between top electrode and TiO_{x}. This leads to higher on/off current ratio and lower operation voltage without degradation of non-linearity which is the important factor for selector-less type ReRAM, compared to the stoichiometric TiN resistor stack. Consequently, it is verified that the switching mechanism is hybrid combination of filament formation and redox reaction in switching operation. This work is applicable to both high density and cost-effective ReRAM.

Threshold Switching and Conductance Quantization in Al/HfO_{2}/Si(p) Structures

2013-03-21T09:00:00+09:00

Authors: Xavier Saura, Enrique Miranda, David Jiménez, Shibing Long, Ming Liu, Joan Marc Rafí, Francesca Campabadal, and Jordi Suñé
Volatile threshold switching and non-volatile memory switching modes of resistive switching are reported in Al/HfO_{2}/Si(p) metal–oxide–semiconductor structures with different values of current compliance limit during electroforming. When the current is limited to below 100 µA, a reproducible threshold switching loop is reported under injection from the p-type silicon substrate. The conduction in the low resistance state is linear above a voltage threshold called holding voltage and the conductance is a non-integer multiple of the quantum of conductance. Depending on the size of the conducting filament created during the electroforming process, one or several quasi-one dimensional quantum subbands are found to contribute to the current. Abrupt transitions between different discrete conductance values are reported during increasing and decreasing voltage sweeps. These results provide strong experimental evidence suggesting that the conduction filament behaves as a quantum wire (QW). No structural instability of the filament has to be invoked to explain either the highly structured conduction properties or the set and reset switching transitions. It is claimed that the whole phenomenology can be understood by electron injection from the valence band into a narrow conducting path which behaves as a QW.

Low-Power and High-Reliability Gadolinium Oxide Resistive Switching Memory with Remote Ammonia Plasma Treatment

2013-03-21T09:00:00+09:00

Authors: Jer-Chyi Wang, Yu-Ren Ye, Jhih-Sian Syu, Pin-Ru Wu, Chih-I Wu, Po-Sheng Wang, and Jung Hung Chang
The effects of remote NH_{3} plasma treatment on a Pt/Gd_{x}O_{y}/W resistive random access memory (RRAM) metal–insulator–metal (MIM) structure were investigated. We found that a decrease in the electron barrier height caused by nitrogen incorporation at the Pt–Gd_{x}O_{y} interface can help reduce the operational set and reset voltages. Nitrogen atoms from the NH_{3} plasma prevent oxygen atoms in the film from diffusing through Pt grain boundaries into the atmosphere, resulting in superior retention properties (>10^{4} s). The stability of the endurance behavior of Gd_{x}O_{y} RRAMs was significantly improved owing to the passivation of defects in Gd_{x}O_{y} films by nitrogen and hydrogen atoms from the remote NH_{3} plasma, markedly reducing plasma damage.

A Column-Parallel Hybrid Analog-to-Digital Converter Using Successive-Approximation-Register and Single-Slope Architectures with Error Correction for Complementary Metal Oxide Silicon Image Sensors

2013-03-21T09:00:00+09:00

Authors: Tsung-Ling Li, Shin Sakai, Shun Kawada, Yasuyuki Goda, Shunichi Wakashima, Rihito Kuroda, and Shigetoshi Sugawa
In this paper, a column-parallel hybrid analog-to-digital converter (ADC) architecture taking the advantages of both successive-approximation-register (SAR) and single-slope (SS) architectures has been developed for CMOS image sensors. The proposed architecture achieves high conversion speed and low power consumption without requiring a high clock frequency and a large number of capacitors. Moreover, an error correction methodology has been presented to calibrate capacitance mismatches in a SAR capacitor array for linearity improvement. An 11-bit hybrid prototype ADC has been implemented in a 0.18-µm 1-poly 5-metal standard CMOS process. The conversion time is 1.225 µs with a maximum operation clock frequency of 40 MHz and it consumes 48 µW. With the proposed error correction, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.40/-0.44 least significant bit (LSB) and +1.21/-1.12 LSB, respectively.

Impact of Body-Biasing Technique on Random Telegraph Noise Induced Delay Fluctuation

Takashi Matsumoto, Kazutoshi Kobayashi, and Hidetoshi Onodera — 2013-03-21T09:00:00+09:00

Authors: Takashi Matsumoto, Kazutoshi Kobayashi, and Hidetoshi Onodera
The statistical nature of random telegraph noise (RTN) induced delay fluctuation is described by measuring 1,655 ROs fabricated in a commercial 40 nm CMOS technology. A small number of samples have a large RTN-induced delay fluctuation. We investigated the impact of the body-biasing technique on RTN-induced circuit delay fluctuation for various substrate bias conditions. The impact of RTN-induced delay fluctuation tends to be reduced by the forward body-biasing technique, but a few ROs still have a large fluctuation.

Dynamic Observation of Brain-Like Learning in a Ferroelectric Synapse Device

Yu Nishitani, Yukihiro Kaneko, Michihito Ueda, Eiji Fujii, and Ayumu Tsujimura — 2013-03-21T09:00:00+09:00

Authors: Yu Nishitani, Yukihiro Kaneko, Michihito Ueda, Eiji Fujii, and Ayumu Tsujimura
A brain-like learning function was implemented in an electronic synapse device using a ferroelectric-gate field effect transistor (FeFET). The FeFET was a bottom-gate type FET with a ZnO channel and a ferroelectric Pb(Zr,Ti)O_{3} (PZT) gate insulator. The synaptic weight, which is represented by the channel conductance of the FeFET, is updated by applying a gate voltage through a change in the ferroelectric polarization in the PZT. A learning function based on the symmetric spike-timing dependent synaptic plasticity was implemented in the synapse device using the multilevel weight update by applying a pulse gate voltage. The dynamic weighting and learning behavior in the synapse device was observed as a change in the membrane potential in a spiking neuron circuit.

125 mW 102.4 GS/s Ultra-High-Speed Sampling Circuit for Complementary Metal–Oxide–Semiconductor Breast Cancer Detection System

Akihiro Toya, Kenta Sogo, Nobuo Sasaki, and Takamaro Kikkawa — 2013-03-21T09:00:00+09:00

Authors: Akihiro Toya, Kenta Sogo, Nobuo Sasaki, and Takamaro Kikkawa
For application to an impulse-radio ultra-wideband (IR-UWB) portable breast cancer detection system, a 102.4 GS/s sampling circuit is developed. The high sampling rate is realized by an equivalent-time sampling technique and a low-power multi-clock generation circuit using a phase interpolator. The phase interpolator achieved a minimum phase resolution 9.8 ps. Using the sampling circuit, a tumor phantom buried by a breast phantom was detected.

A Multi-Pillar Vertical Metal–Oxide–Semiconductor Field-Effect Transistor Type Dynamic Random Access Memory Core Circuit for Sub-1 V Core Voltage Operation without Overdrive Technique

Hyoungjun Na and Tetsuo Endoh — 2013-03-21T09:00:00+09:00

Authors: Hyoungjun Na and Tetsuo Endoh
In this paper, a dynamic random access memory (DRAM) core circuit realizing sub-1 V core voltage operation without using the overdriven sense amplifier technique is proposed by using the multi-pillar vertical MOSFET, and its performance is described with the HSPICE simulation. The proposed DRAM core circuit realizes the same sensing time at 0.6 and 0.75 V lower core supply voltage without and with the overdriven sense amplifier technique, respectively, comparing to the conventional DRAM core circuit by the planar MOSFET with the overdriven sense amplifier technique. Moreover, when V_{CORE} is 1.25 V and V_{DD} is 1.5 V, the overdriven proposed sense amplifier achieves 79% (2.7 ns) faster sensing time than the overdriven conventional sense amplifier. Furthermore, the proposed circuit achieves a faster wordline transition and precharge time than the conventional DRAM core circuit by approximately 17% (1.1 ns) and 55% (0.2 ns), respectively. This proposed DRAM core circuit is a promising circuit technique for low voltage and high speed DRAM core circuit operation.

Electro-Static Discharge Protection Design for V-Band Low-Noise Amplifier Using Radio Frequency Junction Varactor

Ming-Hsien Tsai, Sing-Kai Huang, and Shawn S. H. Hsu — 2013-03-21T09:00:00+09:00

Authors: Ming-Hsien Tsai, Sing-Kai Huang, and Shawn S. H. Hsu
The RF junction varactors are employed as electro-static discharge (ESD) protection devices and co-designed with 60 GHz low-noise amplifier (LNA) fabricated in a 65-nm CMOS technology. The junction varactor acts as an ESD diode to bypass ESD current during ESD zapping, and also utilized as a capacitor to be a part of input matching network of the LNA in normal RF operation. By transmission line pulse (TLP) measurement, the ESD protection capabilities of RF junction varactors are characterized with different device parameters. The experimental results demonstrate excellent second breakdown currents (I_{t2}) and high ratios of the ESD levels to parasitic capacitances (V_{ESD}/C_{ESD}). With ESD/matching co-design methodology, the ESD-protected LNA demonstrates a second breakdown current I_{t2} of 1.4 A, corresponding to a 2-kV human-body-model (HBM) ESD protection level with a noise figure (NF) of 6.6 dB and a peak gain of 16.5 dB at 60 GHz under a power consumption of only 28 mW.

Side-Illuminated Color Photosensor

Tetsuya Ariyoshi, Akiyoshi Baba, and Yutaka Arima — 2013-03-21T09:00:00+09:00

Authors: Tetsuya Ariyoshi, Akiyoshi Baba, and Yutaka Arima
We have proposed a simple method for color imaging in which the photosensor is illuminated from the side. In this method, color imaging can be produced using single pixels and without generating false colors and moiré patterns. A 5.0 ×5.0 mm^{2} test chip was fabricated using a 0.35 µm complementary metal oxide semiconductor (CMOS) 1-poly 4-metal process. Because the side illumination method is used, the side of the test chip was etched using a high-speed deep reactive ion etching (D-RIE) process. Light illumination experiments confirmed that four colors – blue, green, red, and near-infrared – could be separated using this method. We also estimated the color separation properties of a similar sensor based on a 0.18 µm CMOS process.

Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm

Zuoxun Hou, Yitao Ma, Hongbo Zhu, Nanning Zheng, and Tadashi Shibata — 2013-03-21T09:00:00+09:00

Authors: Zuoxun Hou, Yitao Ma, Hongbo Zhu, Nanning Zheng, and Tadashi Shibata
A very large-scale integration (VLSI) recognition system equipped with an on-chip learning capability has been developed for real-time processing applications. This system can work in two functional modes of operation: adaptive K-means learning mode and recognition mode. In the adaptive K-means learning mode, the variance ratio criterion (VRC) has been employed to evaluate the quality of K-means classification results, and the evaluation algorithm has been implemented on the chip. As a result, it has become possible for the system to autonomously determine the optimum number of clusters (K). In the recognition mode, the nearest-neighbor search algorithm is very efficiently carried out by the fully parallel architecture employed in the chip. In both modes of operation, many hardware resources are shared and the functionality is flexibly altered by the system controller designed as a finite-state machine (FSM). The chip is implemented on Altera Cyclone II FPGA with 46K logic cells. Its operating clock is 25 MHz and the processing times for adaptive learning and recognition with 256 64-dimension feature vectors are about 0.42 ms and 4 µs, respectively. Both adaptive K-means learning and recognition functions have been verified by experiments using the image data from the COIL-100 (Columbia University Object Image Library) database.

Dual Data Pulse Width Modulator for Radio Frequency Identification Biosensor Signal Modulation

Boram Kim and Kazuo Nakazato — 2013-03-21T09:00:00+09:00

Authors: Boram Kim and Kazuo Nakazato
A dual data pulse width modulator is proposed and demonstrated for radio frequency identification (RFID) biosensor signal modulation. Simultaneous wireless measurement of two sensors can be carried out using this circuit, in which two analog signals are modulated and transmitted in a single clock cycle. The measured modulation sensitivity of the two input channels is 84.69 and 85.16 µs/V and the dynamic range is 55.6 and 63.5 dB, respectively. Here, redox potential and temperature are measured wirelessly using the proposed circuit. Temperature change measurement shows a sensitivity of 9.501 µs/°C in the range of 25–40 °C. The measured redox potential shows fairly good linearity for a concentration ratio of hexacyanoferrate (III) to (II) ranging from 10^{-2} to 10^{2} and the slope is 58.0 mV/decade, almost the same as the theoretical value. The chip area and power consumption are 0.36 mm^{2} and 650 µW, respectively, using 1.2-µm, 2-metal, 2-poly CMOS technology.

High Open-Circuit Voltage Gain in Vertical InGaAs Channel Metal–Insulator–Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region and Narrow Channel Mesa

2013-03-21T09:00:00+09:00

Authors: Masashi Kashiwano, Jun Hirai, Shunsuke Ikeda, Motohiko Fujimatsu, and Yasuyuki Miyamoto
We fabricated a vertical metal–insulator–semiconductor field-effect transistor (MISFET) with a heterostructure launcher and an undoped channel. Vertical MISFETs exhibit a high drain current density; however, their large output conductance is a disadvantage for the open-circuit voltage gain. In a previous study, a maximum voltage gain of 4.0 was found in a vertical MISFET with a heavily doped drain region and a 45-nm-wide channel mesa. The heavily doped drain region and a narrower channel width are effective in reducing the output conductance. In this study, we fabricated a device with the heavily doped drain region and a 23-nm-wide channel mesa structure. It was observed that the output conductance decreased from 120 to 57 mS/mm at a drain current density of 0.3 MA/cm^{2} with a narrower channel mesa. The maximum open-circuit voltage gain increased from 4.0 to 5.7.

AlGaN/GaN Metal–Oxide–Semiconductor High-Electron-Mobility Transistors with a High Breakdown Voltage of 1400 V and a Complementary Metal–Oxide–Semiconductor Compatible Gold-Free Process

2013-03-21T09:00:00+09:00

Authors: Xinke Liu, Chunlei Zhan, Kwok Wai Chan, Man Hon Samuel Owen, Wei Liu, Dong Zhi Chi, Leng Seow Tan, Kevin Jing Chen, and Yee-Chia Yeo
This paper reports the fabrication and characterization of AlGaN/GaN-on-sapphire metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) using a complementary metal–oxide–semiconductor (CMOS) compatible gold-free process. Devices with a gate-to-drain spacing L_{GD} of 20 µm achieved an off-state breakdown voltage V_{BR} of 1400 V and an on-state resistance R_{on} of 22 mΩ·cm^{2}. This is the highest V_{BR} achieved so far for gold-free AlGaN/GaN MOS-HEMTs. In addition, high on/off current ratio I_{on}/I_{off} of ∼10^{9} and low gate leakage current I_{G} of ∼10^{-11} A/mm were also obtained.

Effects of Deep Trapping States at High Temperatures on Transient Performance of AlGaN/GaN Heterostructure Field-Effect Transistors

Kenichiro Tanaka, Masahiro Ishida, Tetsuzo Ueda, and Tsuyoshi Tanaka — 2013-03-21T09:00:00+09:00

Authors: Kenichiro Tanaka, Masahiro Ishida, Tetsuzo Ueda, and Tsuyoshi Tanaka
Kinetic studies on the current collapse of a normally-OFF AlGaN/GaN heterostructure field-effect transistor under a high voltage have been performed above room temperature. The ON-state resistance after the ON switching from the OFF state increases at high temperatures, contrary to the expectation that the emission of electrons is enhanced at elevated temperatures. This result indicates that elevating the temperature enhances not only the emission of electrons but also their capture. We experimentally observe that the enhancement of the capture process at high temperatures originates from the energy barrier for the capture of electrons, the value of which is determined to be 0.17±0.04 eV. The origin of the energy barrier for the capture process is explained by a configuration coordinate diagram.

Improvement of Current Collapse by Surface Treatment and Passivation Layer in p-GaN Gate GaN High-Electron-Mobility Transistors

2013-03-21T09:00:00+09:00

Authors: Takashi Katsuno, Masakazu Kanechika, Kenji Itoh, Koichi Nishikawa, Tsutomu Uesugi, and Tetsu Kachi
The improvement of current collapses of p-GaN gate GaN high-electron-mobility transistors (HEMTs) caused by the effects of surface treatment and the passivation layer was investigated. The NH_{3} treatment and high-temperature oxide (HTO) passivation layer on the AlGaN layer are effective in improving the current collapse of a p-GaN gate GaN HEMT. The current collapse at a long time constant (τ= 4 s) could be decreased by the NH_{3} treatment of the AlGaN layer, because the nitrogen atoms in nitrogen vacancies in the AlGaN layer (trap level: 0.6 eV) would be incorporated, resulting in a low surface density. The current collapse at an intermediate time constant (τ= 11 ms) could also be decreased by the deposition of the HTO passivation layer on the AlGaN layer, because the low-interface-density layer (trap level: 0.4 eV) of HTO/AlGaN would be formed.

High Quality SiO_{2}/Al_{2}O_{3} Gate Stack for GaN Metal–Oxide–Semiconductor Field-Effect Transistor

2013-03-21T09:00:00+09:00

Authors: Hiroshi Kambayashi, Takehiko Nomura, Hirokazu Ueda, Katsushige Harada, Yuichiro Morozumi, Kazuhide Hasebe, Akinobu Teramoto, Shigetoshi Sugawa, and Tadahiro Ohmi
High quality SiO_{2}/Al_{2}O_{3} gate stack has been demonstrated for GaN metal–oxide–semiconductor (MOS) transistor. We confirmed that Al_{2}O_{3} could realize a low interface-state density between Al_{2}O_{3} and GaN, however, the breakdown field was low. By incorporating the merits of both Al_{2}O_{3} and SiO_{2}, which has a high breakdown field and a large charge-to-breakdown, SiO_{2}/Al_{2}O_{3} gate stack structure has been employed in GaN MOS devices. The structure shows a low interface state density between gate insulator and GaN, a high breakdown field, and a large charge-to-breakdown. The SiO_{2}/Al_{2}O_{3} gate stack has also been applied to AlGaN/GaN hybrid MOS heterojunction field-effect transistor (HFET). The MOS-HFET shows excellent properties with the threshold voltage of 4.2 V and the maximum field-effect mobility of 192 cm^{2} V^{-1} s^{-1}.

Fully Transparent Al-Doped ZnO Thin-Film Transistors on Flexible Plastic Substrates

2013-03-21T09:00:00+09:00

Authors: Wei Wang, Dedong Han, Jian Cai, Youfeng Geng, Liangliang Wang, Longyan Wang, Yu Tian, Xing Zhang, Yi Wang, and Shengdong Zhang
We have fabricated fully transparent Al-doped ZnO thin-film transistors (AZO TFTs) on a flexible plastic substrate at room temperature. A double-stacked channel structure composed of a high-density layer and a low-density layer is also investigated to improve the device performance. As-fabricated TFTs exhibit excellent electrical performance as well as optical performance, with a saturation mobility of 31.4 cm^{2} V^{-1} s^{-1}, a drain current on/off ratio of about 10^{8}, a subthreshold swing of 330 mV/dec, and an average transmittance in the visible wavelength range of above 70%.

Effect of O_{2} Incorporation During the Channel Fabrication Process on Aluminum-Doped Zinc Oxide Thin-Film Transistor Characteristics

2013-03-21T09:00:00+09:00

Authors: Jian Cai, Dedong Han, Youfeng Geng, Wei Wang, Liangliang Wang, Yu Tian, Lixun Qian, Xing Zhang, Shengdong Zhang, and Yi Wang
High-performance aluminum-doped zinc oxide thin-film transistors (AZO TFTs) have been successfully fabricated on glass substrates. By controlling the oxygen flow ratio (OFR) during the deposition of an AZO active layer, we have demonstrated that the incorporation of oxygen in the deposition atmosphere plays an important role in improving the electronic performance of TFTs. For gate voltage V_{G} = -2 to 5 V, the TFTs with an AZO active layer sputter deposited in an atmosphere of Ar and O_{2} mixture at room temperature (RT) as the channel layer exhibit much better properties than TFTs whose AZO layer was deposited in pure Ar atmosphere, such as a high saturation mobility (µ_{sat}) of 113 cm^{2} V^{-1} s^{-1}, a positive threshold voltage V_{th} of 1.5 V, an improved steep subthreshold swing from 400 to 125 mV/decade, a decreased off-state current (I_{off}) from 10^{-8} to 5×10^{-13} A, an increased on/off ratio from 10^{5} to 10^{9}, and a higher transmittance of 82.5%.

Design of Silicon Photonic Crystal Waveguides for High Gain Raman Amplification Using Two Symmetric Transvers-Electric-Like Slow-Light Modes

Yi-Hua Hsiao, Satoshi Iwamoto, and Yasuhiko Arakawa — 2013-03-21T09:00:00+09:00

Authors: Yi-Hua Hsiao, Satoshi Iwamoto, and Yasuhiko Arakawa
We designed silicon photonic crystal (PhC) waveguides (WGs) for efficient silicon Raman amplifiers and lasers. We adopted narrow-width WGs to utilize two symmetric transvers-electric-like (TE-like) guided modes, which permit efficient external coupling for both the pump and Stokes waves. Modifying the size and shape of air holes surrounding the line-defect WG structures could tune the frequency difference between these two modes, at the Brillouin-zone edge, to match the Raman shift of silicon. Thus, small group velocities are also available both for pump and Stokes waves simultaneously, which results in a large enhancement of Raman gain. The enhancement factor of the Raman gain in the designed structure is more than 100 times that reported previously.

GaAs/AlAs Multilayer Cavity with Er-Doped InAs Quantum Dots Embedded in Thin Strain-Relaxed In_{0.45}Ga_{0.55}As Barriers for Ultrafast All-Optical Switches

2013-03-21T09:00:00+09:00

Authors: Ken Morita, Huga Ueyama, Yukinori Yasunaga, Yoshinori Nakagawa, Takahiro Kitada, and Toshiro Isu
A GaAs/AlAs multilayer cavity with a λ/2 AlAs cavity layer, which includes Er-doped InAs quantum dots (QDs) embedded in a thin strain-relaxed In_{0.45}Ga_{0.55}As barrier, was fabricated. Structural and optical properties were characterized by scanning electron microscopy and optical reflection measurements, respectively. We found that the cavity quality of the Er-doped QD cavity was improved by reducing the thickness of the strain-relaxed In_{0.45}Ga_{0.55}As barriers in the λ/2 AlAs cavity layer. Furthermore, time-resolved optical measurements were performed to study the relaxation time of the photogenerated carriers in the Er-doped QD cavity. A full width at half maximum of a 1 ps with a large reduction of slowly decaying carriers was obtained for the Er-doped QD cavity with a thin strain-relaxed In_{0.45}Ga_{0.55}As barrier.

Thermal Conductive Properties of a Semiconductor Laser on a Polymer Interposer

2013-03-21T09:00:00+09:00

Authors: Takeru Amano, Shigenari Ukita, Laina Ma, Masahiro Aoyagi, Takeyoshi Sugaya, and Kazuhiro Komori
We have calculated the thermal conductive properties and rate of temperature increase of a semiconductor laser on a polymer substrate. The temperature rises to 27 °C on the polymer interposer and the heat radiation effect is almost saturated in the case where the Au film has a thickness of 500 nm at 10 mW. Also, we have fabricated a 1.3 µm quantum dot (QD) laser with a stripe structure for the polymer interposer. We can achieve a low operating current threshold of 7 mA for the QD laser with a high mirror loss of 16 cm^{-1} at 1.3 µm emission because of the high quality of the QDs and the low scattering loss structure. Moreover, we have measured the heat distribution and rising temperature speed of a QD laser on a polymer substrate. These results indicate that we need to realize a high-efficiency laser source to achieve high transmission speeds in the future.

A GaAs/Air Multilayer Cavity for a Planar-Type Nonlinear Optical Device

2013-03-21T09:00:00+09:00

Authors: Hidetada Komatsu, Zhao Zhang, Yoshinori Nakagawa, Ken Morita, Takahiro Kitada, and Toshiro Isu
GaAs/air multilayer cavity structure is expected as a novel planar-type nonliner optical device because of the strong enhancement of optical electric fileds in the cavity. The optical Kerr signal was estimated to be two order of magnitude larger than that from GaAs/AlAs multilayer cavity with the same Q-value by numerical simulation. We fabricated a GaAs/air cavity structure with 2-period distributed Bragg reflector (DBR) layers on each side of the λ-cavity layer by wet etching of sacrificial AlGaAs layer. Measured reflection spectra showed the expected structure was successfully fabricated in some parts.

Over 1.5 µm Deep Dry Etching of Al-Rich AlGaAs for Photonic Crystal Fabrication

Yuta Kitabayashi, Masaya Mochizuki, Fumitaro Ishikawa, and Masahiko Kondow — 2013-03-21T09:00:00+09:00

Authors: Yuta Kitabayashi, Masaya Mochizuki, Fumitaro Ishikawa, and Masahiko Kondow
We investigate inductively coupled plasma deep dry etching of Al_{0.8}Ga_{0.2}As for photonic crystal (PC) fabrication using the Cl_{2}, BCl_{3}, and CH_{4} mixture. On the basis of our previous work [M. Mochizuki et al.: Jpn. J. Appl. Phys. 50 (2011) 04DG15], we explore the deeper dry etching of the PC structure, investigating the impact of gas flow rate and chemical reactions. Increasing gas flow rate and process pressure resulted in deeper etching. These conditions increased the self-bias applied on the sample, which induced the sharpening of the air hole bottom and limitation of further deep etching because of the strong contribution of physical etching. The reduction of CH_{4} gas suppressed the sidewall passivation, counteracting the effect of the physical etching. As a result, we obtained a PC structure having air holes with a depth larger than 1.5 µm and a diameter of 120 nm.

Optically Pumped Lasing Action with Unusual Wavelength of Approximately 390 nm in Hexagonal GaN Microdisks Fabricated by Radio-Frequency Plasma-Assisted Molecular Beam Epitaxy

Tetsuya Kouno, Masaru Sakai, Katsumi Kishino, and Kazuhiko Hara — 2013-03-21T09:00:00+09:00

Authors: Tetsuya Kouno, Masaru Sakai, Katsumi Kishino, and Kazuhiko Hara
Hexagonal GaN microdisks exhibiting lasing action with unusual wavelengths of approximately 390 nm under an optically pumped condition have been investigated. The lasing action was caused by the resonant modes of the whispering gallery mode and/or quasi-whispering gallery mode in the hexagonal microdisks. A cross-sectional transmission electron microscopy observation indicated that multiple crystalline boundaries, which are formed by stacking faults, were included in the specific GaN microdisks exhibiting such an unusual lasing action. The origin of the optical gain was discussed, based on the modification of the crystal structure associated with the stacking faults.

Channel Length Scaling and Surface Nitridation of Silicon Nanocrystals for High-Performance Electron Devices

2013-03-21T09:00:00+09:00

Authors: Susoma Jannatul Ferdous, Yoshifumi Nakamine, Tetsuo Kodera, Koichi Usami, Yukio Kawano, and Shunri Oda
Silicon nanocrystal (SiNC)-based thin-film devices have been fabricated, where the idea of scaling down of channel length was implemented in such a way that very few SiNCs can be fitted inside the channel in the channel length direction in order to decrease the number of barriers to increase electrical conductivity. In this study, we have demonstrated the scaling down of channel length to 20 nm in order to reduce the number of barriers provided by each of the SiNCs, which are fabricated using a very high-frequency (VHF) plasma-enhanced chemical vapor deposition (CVD) system with a diameter of 10±1 nm. A high electrical conductivity has been achieved by optimizing channel length. In addition, we have demonstrated the surface nitridation of SiNCs to protect the highly reactive surface of SiNCs from further natural oxidization and successfully suppressed the degradation of transport properties.

Growth of (111) One-Axis-Oriented Bi(Mg_{1/2}Ti_{1/2})O_{3} Films on (100)Si Substrates

2013-03-21T09:00:00+09:00

Authors: Takahiro Oikawa, Shintaro Yasui, Takayuki Watanabe, Koji Ishii, Yoshitaka Ehara, Hisato Yabuta, Takeshi Kobayashi, Tetsuro Fukui, Kaoru Miura, and Hiroshi Funakubo
Films of a high-pressure perovskite phase, Bi(Mg_{1/2}Ti_{1/2})O_{3}, were prepared on (111)_{c}-oriented SuRuO_{3}-coated (111)Pt/TiO_{2}/SiO_{2}/(100)Si substrates. The perovskite Bi(Mg_{1/2}Ti_{1/2})O_{3} films had a (111) one-axis orientation, because their constituent grains were epitaxially grown on (111)_{c}-oriented perovskite SrRuO_{3} ones. The remanent polarization and piezoelectric constant measured at an applied electric field of 600 kV/cm were about 30 µC/cm^{2} and 40 pm/V, respectively. A remarkable phase transition was not observed from room temperature to 350 °C in a (111) one-axis-oriented Bi(Mg_{1/2}Ti_{1/2})O_{3} film, suggesting that the Curie temperature of this film is above 350 °C.

Disorder-Induced Enhancement of Avalanche Multiplication in a Silicon Nanodot Array

2013-03-21T09:00:00+09:00

Authors: Nobuya Mori, Masanori Tomita, Hideki Minari, Takanobu Watanabe, and Nobuyoshi Koshida
Impacts of atomic disorder on avalanche multiplication in a one-dimensional silicon nanodot (SiND) array have been theoretically studied. The disorder lifts the degeneracy of the energy levels and reduces the impact-ionization threshold. This leads to a larger carrier multiplication factor in the disordered SiND array compared to an ideal SiND array without disorder or strain.

Integration of Complementary Metal–Oxide–Semiconductor 1-Bit Analog Selectors and Single-Electron Transistors Operating at Room Temperature

Ryota Suzuki, Motoki Nozue, Takuya Saraya, and Toshiro Hiramoto — 2013-03-21T09:00:00+09:00

Authors: Ryota Suzuki, Motoki Nozue, Takuya Saraya, and Toshiro Hiramoto
Silicon-based single-electron transistors (SETs) and complementary metal–oxide–semiconductor (CMOS) devices have been integrated onto a single chip, and the operation of SET/CMOS integrated circuits has been demonstrated at room temperature. The fabrication process of SETs has been improved in terms of parasitic resistance suppression, threshold voltage control, and reduction in required time for electron-beam lithography for integration with CMOS devices. There is no significant degradation in the characteristics of CMOS devices owing to the special fabrication process of SETs operating at room temperature. CMOS 1-bit analog selectors, which are building blocks of multibit address decoders, have been combined with SETs, and the circuit operation has been demonstrated at room temperature for the first time. These results show the feasibility of SET/CMOS integrated circuits composed of high-density arrays of SETs and high-performance CMOS peripheral circuits, which fully leverage the advantages of SETs and CMOS.

Influence of Coulomb Blockade on Wave Packet Dynamics in Nanoscale Structures

2013-03-21T09:00:00+09:00

Authors: Taro Shiokawa, Genki Fujita, Yukihiro Takada, Satoru Konabe, Masakazu Muraguchi, Takahiro Yamamoto, Tetsuo Endoh, Yasuhiro Hatsugai, and Kenji Shiraishi
Influence of Coulomb blockade on electron scattering by a quantum dot has been theoretically investigated using a multielectron wave packet simulation technique based on the time-dependent Hartree–Fock approximation. In our simulation, the bound states of electrons in the dot are self-consistently determined. We confirmed that Koopman's theorem keeps its validity only for weak Coulomb interactions. Moreover, we show that the maximum number of electrons trapped in the dot does depend on the strength of Coulomb interactions. Consequently, the transmission and reflection probabilities of an incident wave packet toward the dot are strongly influenced by the number of trapped electrons in the dot.

Resistance Switching Memory Characteristics of Si/CaF_{2}/CdF_{2} Quantum-Well Structures Grown on Metal (CoSi_{2}) Layer

Junya Denda, Kazuya Uryu, and Masahiro Watanabe — 2013-03-21T09:00:00+09:00

Authors: Junya Denda, Kazuya Uryu, and Masahiro Watanabe
A novel scheme of resistance switching random access memory (ReRAM) devices fabricated using Si/CaF_{2}/CdF_{2}/CaF_{2}/Si quantum-well structures grown on metal CoSi_{2} layer formed on a Si substrate has been proposed, and embryonic write/erase memory operation has been demonstrated at room temperature. It has been found that the oxide-mediated epitaxy (OME) technique for forming the CoSi_{2} layer on Si dramatically improves the stability and reproducibility of the current–voltage (I–V) curve. This technology involves 10-nm-thick Co layer deposition on a protective oxide prepared by boiling in a peroxide-based solution followed by annealing at 550 °C for 30 min for silicidation in ultrahigh vacuum. A switching voltage of lower than 1 V, a peak current density of 32 kA/cm^{2}, and an ON/OFF ratio of 10 have been observed for the sample with the thickness sequence of 0.9/0.9/2.5/0.9/5.0 nm for the respective layers in the Si/CaF_{2}/CdF_{2}/CaF_{2}/Si structure. Results of surface morphology analysis suggest that the grain size of crystal islands with flat surfaces strongly affects the quality of device characteristics.

Nanogap Resistance Random Access Memory Based on Natural Aluminum Oxide

Toru Miyabe and Toshihiro Nakaoka — 2013-03-21T09:00:00+09:00

Authors: Toru Miyabe and Toshihiro Nakaoka
We report unipolar and bipolar resistive switchings in naturally oxidized Al_{x}O_{1-x} thin films. We find a relationship between the switching behavior and the electrode gap distance. The macro-gap device with the electrode separation of 20 µm shows a unipolar switching behavior while the nano-gap device with the separation of 40 nm shows a bipolar behavior. The result is explained by a model in which the unipolar or the bipolar switching is governed by the way of the carrier injection into oxygen vacancies.

A Numerical Device Model and Approach to Degradation Mechanisms in Organic Light Emitting Diodes

Tadahiko Hirai, Karl Weber, Jenny O’Connell, Mark Bown, and Kazunori Ueno — 2013-03-21T09:00:00+09:00

Authors: Tadahiko Hirai, Karl Weber, Jenny O’Connell, Mark Bown, and Kazunori Ueno
We propose a novel Schottky and impedance spectroscopy (IS) numerical model to evaluate carrier injection and transport behavior of organic semiconductor materials. Using temperature-dependent current–voltage (I–V) and IS measurements of hole-only (HOD) and electron-only (EOD) devices and phosphorescent blue organic light emitting diodes (OLEDs), we have obtained values for the Richardson factor, the barrier height, trap density, density of states (DOS), and carrier mobility of organic materials and interfaces as device parameters. Therefore, we approach to degradation mechanism of the emitting zone inside of the OLEDs.

Efficient Solution-Processed Green Phosphorescent Organic Light-Emitting Diodes Using Bipolar Host Material

2013-03-21T09:00:00+09:00

Authors: Yu-Sheng Tsai, Apisit Chittawanij, Fuh-Shyang Juang, Lin-Ann Hong, and Chih-Yuan Ou
Solution-based processing was applied to fabricate green phosphorescent organic light-emitting diodes (OLEDs). EPH31 was used as a phosphorescent host, doped with guest dopant green phosphorescent Ir(ppy)_{3}, and dissolved in chlorobenzene solvent to form the emitting layer. Device structural parameters were controlled by changing the spin coating speed of the emitting layer and hole injection layer [poly(3,4-ethylene dioxythiophene):poly(styrene sulfonate), PDOT:PSS] to adjust the thickness of the electron transport layer [tris(8-hydroxyquinolinato)aluminum, Alq_{3}]. In addition, the differences in using CsF and LiF materials as the electron injection layer were investigated. A maximum current efficiency of 13.6 cd·A^{-1} was obtained at a high emitting layer spin coating speed. Despite the close resemblance in both the luminance intensity and current efficiency when using CsF and LiF as the electron injection layer, CsF devices had a low driving voltage. Smooth and stable films resulting from the spin coated hole injection layer, along with the control of the thickness of the electron transport layer (Alq_{3}) and electron injection layer (CsF), effectively improved the performance of green OLEDs. The emitting layer host material (CBP) and three guest dopants [Firpic, Ir(ppy)_{3}, and Ir(piq)_{2}] were dissolved in toluene solvent during solution preparation to fabricate white OLEDs. The properties of the resulting solution-processed white PHOLEDs are a current efficiency of 2.4 cd·A^{-1} at 20 mA·cm^{-2} and CIE coordinates of (0.33, 0.33) at 9 V. Results of these experiments demonstrate that solution processing can be used as an alternative to and in conjunction with thermal evaporation.

A Novel Microscope for Visualizing Electric Fields in Organic Thin Film Devices Using Electric-Field-Induced Second-Harmonic Generation

2013-03-21T09:00:00+09:00

Authors: Dai Taguchi, Takaaki Manaka, Mitsumasa Iwamoto, Tetushu Karasuda, and Mikio Kyomasu
We have developed a novel microscope for visualizing electric fields in organic thin film devices on the basis of electric-field-induced second-harmonic generation (EFISHG) measurement. By using a radial polarized laser beam as a probing light, we showed that the electric field formed in metal–C_{60}–metal diodes in the film-thickness direction is visualized. The developed microscope has a potentiality in directly visualizing carrier motion in thin-film devices such as organic solar cells.

Photovoltaic Properties of Bulk-Heterojunction Organic Solar Cell with Ultrathin Titanium Oxide Nanosheet as Electron Selective Layer

Eiji Itoh, Yasutake Maruyama, and Katsutoshi Fukuda — 2013-03-21T09:00:00+09:00

Authors: Eiji Itoh, Yasutake Maruyama, and Katsutoshi Fukuda
The contributions of ultrathin titania nanosheet (TN) crystallites were studied in both an inverted bulk-heterojunction (BHJ) cell in indium tin oxide (ITO)/titania nanosheet (TN)/poly(3-hexylthiophene) (P3HT):phenyl-C_{61}-butyric acid methylester (PCBM) active layer/MoO_{3}/Ag and a conventional BHJ cell in ITO/MoO_{3}/P3HT:PCBM active layer/TN/Al multilayered photovoltaic devices. The insertion of only one or two layers of poly(diallyldimethylammonium chloride) (PDDA) and TN multilayered film prepared by the layer-by-layer deposition technique effectively decreased the leakage current and increased the open circuit voltage (V_{OC}), fill factor (FF), and power conversion efficiency (η). The abnormal S-shaped curves observed in the inverted BHJ cell above V_{OC} disappeared with the reduction in the work function of the bottom electrode in the inverted cells. The power conversion efficiency was increased nearly twofold, and better photovoltaic performance was observed in the conventional BHJ cells. Although the active layer has a hydrophobic surface, the active layer was fully covered by the insertion of only two or three layers of PDDA/TN multilayered film. The TN layer effectively decreased the leakage current by a factor of 100, and increased the open circuit voltage by 0.25 V probably owing to the complete hole blocking at the P3HT/TN/Al interface.

Development of Plasmon Resonance Sensing Based on Alkylthiol-Coated Triangular Silver Nanoplates on Glass Plates

Kosuke Sugawa, Daido Tanaka, Tomonori Ichikawa, and Naoto Takeshima — 2013-03-21T09:00:00+09:00

Authors: Kosuke Sugawa, Daido Tanaka, Tomonori Ichikawa, and Naoto Takeshima
In this study, we have developed localized surface plasmon resonance (LSPR) refractive index sensor systems consisting of triangular silver nanoplates (nanoprisms) immobilized on glass plates by electrostatic interactions. The nanoprisms are synthesized by exploiting light-induced morphological changes in silver nanoparticles in aqueous solution. We have demonstrated that silver nanoprisms protected with alkylthiol molecules and supported by glass plates can function as spectrally stable LSPR refractive index sensors even in ethanol solvents. The sensitivity of the nanoprisms was found to increase with decreasing carbon chain length of alkylthiol. Furthermore, we have demonstrated that nanoprisms with higher aspect ratios had higher sensitivities than those with lower aspect ratios.

Photocurrent Enhancement in Porphyrin–Silver Nanoparticle Composite Films Using Nanostructures of Silver Nanoparticles

Ryuji Matsumoto, Sunao Yamada, and Hiroaki Yonemura — 2013-03-21T09:00:00+09:00

Authors: Ryuji Matsumoto, Sunao Yamada, and Hiroaki Yonemura
The fabrication of tetraphenyl porphyrin (TPP)–silver nanoparticle (AgP) composite films on indium–tin oxide (ITO) electrodes was carried out by the electrostatic layer-by-layer adsorption technique. Maximum enhancement in photocurrent action spectra as well as in fluorescence emission spectra was observed at an immersion time of 2 h. The effects of AgP on photocurrent and fluorescence suggested the effects of enhanced electric fields resulting from a localized surface plasmon resonance on the enhancement of photocurrent and fluorescence signals. The effect of AgP on the lifetime of the singlet excited state of TPP (^{1}TPP^{*}) indicated that the lifetime of ^{1}TPP^{*} decreases as compared with that in the absence of AgP substrate. The results on fluorescence lifetime suggested that the difference between the effects of AgP on photocurrent and fluorescence is most likely ascribed to the notion that the energy transfer from ^{1}TPP^{*} to surface plasmons due to AgP aggregates competes with photoinduced electron transfer from ^{1}TPP^{*} to O_{2} during photocurrent measurement.

Three-Dimensional Simulation of DNA Sensing by Ion-Sensitive Field-Effect Transistor: Optimization of DNA Position and Orientation

Yuki Nishio, Shigeyasu Uno, and Kazuo Nakazato — 2013-03-21T09:00:00+09:00

Authors: Yuki Nishio, Shigeyasu Uno, and Kazuo Nakazato
Full three-dimensional simulation of DNA detection by ion-sensitive field-effect transistor technology is presented. DNA conditions for improving the sensing characteristics, namely, increased hybridization signal, are clarified. Poisson's equation is solved using a full three-dimensional finite element method for the model, where the model space consists of an electrolyte, DNAs, a self-assembled monolayer, and an insulator. The flatband voltage shift due to the hybridization of randomly positioned and oriented DNA is similar to experimental data, and indicates the possibility of experimental prediction. We examine the effects of DNA position and orientation on flatband voltage shift, and it is noted that the hybridization signal becomes largest when the DNAs are tilted 90° and distributed at equal intervals. It is also noted that a large hybridization signal can be obtained when upright DNAs are tightly immobilized even if it is difficult to tilt the DNAs.

Biomimetic Trehalose Biosensor Using Gustatory Receptor (Gr5a) Expressed in Drosophila Cells and Ion-Sensitive Field-Effect Transistor

2013-03-21T09:00:00+09:00

Authors: Hui-Chong Lau, Tae-Eon Bae, Hyun-June Jang, Jae-Young Kwon, Won-Ju Cho, and Jeong-Ok Lim
The development of potential applications of biosensors using the sensory systems of vertebrates and invertebrates has progressed rapidly, especially in clinical diagnosis. The biosensor developed here involves the use of Drosophila cells expressing the gustatory receptor Gr5a and an ion-sensitive field-effect transistor (ISFET) sensor device. Gustatory receptor Gr5a is expressed abundantly in gustatory neurons and acts as a primary marker for tastants, especially sugar, in Drosophila. As a result, it could potentially serve as a good candidate for potential biomarkers of diseases in which the current knowledge of the cause and treatment is limited. The developed ISFET was based on the outstanding electrical characteristics of the metal–oxide–semiconductor field-effect transistor (MOSFET) with a subthreshold swing of 85 mV/dec, low leakage current of <10^{-12} and high on/off current ratio of 7.3×10^{6}. The SiO_{2} sensing membrane with a pH sensitivity of 34.9 mV/pH and drift rate 1.17 mV/h was sufficient for biosensing applications. In addition, the sensor device also showed significant compatibility with the Drosophila cells expressing Gr5a and their response to sugar, particularly trehalose. Moreover, the interactions between the transfected Drosophila cells and trehalose were consistent and reliable. This suggests that the developed ISFET sensor device could have potential use in the future as a screening device in diagnosis.

Effects of Interface Resistance Asymmetry on Local and Non-local Magnetoresistance Structures

2013-03-21T09:00:00+09:00

Authors: Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Mizue Ishikawa, and Yoshiaki Saito
Spin injection and detection are very sensitive to the interface properties between ferromagnet and semiconductor. Because the interface properties such as a tunneling resistance and a polarization factor can be chosen independently between the injection and detection sides, the magnetic transport properties are considered to depend on the asymmetry of the two interfaces. We theoretically investigate the effect of the asymmetric interfaces of the injection side and the detection side on both the local and non-local magnetoresistance measurements. The results show the magnetoresistance ratio of local measurement structure has its maximum at the symmetric structure, and the effect of the asymmetry is very weak for the non-local measurement structure.

A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure

Daisuke Suzuki, Yuhui Lin, Masanori Natsui, and Takahiro Hanyu — 2013-03-21T09:00:00+09:00

Authors: Daisuke Suzuki, Yuhui Lin, Masanori Natsui, and Takahiro Hanyu
A single-ended circuit using three-terminal magnetic tunnel junction (3T-MTJ) devices is proposed for a compact nonvolatile lookup-table (NV-LUT) circuit. The use of 3T-MTJ devices makes a high tunnel magneto-resistance ratio used in the circuit, because read-current path is separated from the write-current path. By utilizing single-ended circuit structure, the NV-LUT circuit becomes quite simple without reference circuit. In fact, the effective area of the proposed 6-input NV-LUT circuit is only 29% the size of the corresponding CMOS-based implementation using two-terminal-MTJ-based nonvolatile static random access memory cells, with a simulation program with integrated circuit emphasis (SPICE) simulation under a 90 nm CMOS technology.

Picosecond Carrier Spin Relaxation in In_{0.8}Ga_{0.2}As/AlAs/AlAs_{0.56}Sb_{0.44} Coupled Double Quantum Wells

2013-03-21T09:00:00+09:00

Authors: Ryo Yamaguchi, Shin-ichiro Gozu, Teruo Mozume, Yoshitsugu Oyanagi, Mitsunori Uemura, and Atsushi Tackeuchi
The carrier spin relaxation of In_{0.8}Ga_{0.2}As/AlAs/AlAs_{0.56}Sb_{0.44} coupled double quantum wells is investigated by spin-dependent pump and probe reflectance measurements with a high time resolution of 200 fs. The observed fast spin relaxation time of 9 ps at room temperature indicates high potential for applications to high-speed optical devices. A negative temperature dependence of spin relaxation time is observed between 100 K and room temperature. The spin relaxation is found to be governed by the Bir–Aronov–Pikus process between 10 and 100 K and by the D'yakonov–Perel' and Elliott–Yafet processes between 100 K and room temperature.

Molecular Beam Epitaxy of Co_{2}MnSi Films on Group-IV Semiconductors

2013-03-21T09:00:00+09:00

Authors: Makoto Kawano, Shinya Yamada, Soichiro Oki, Kohei Tanikawa, Masanobu Miyao, and Kohei Hamaya
We explore epitaxial growth of Co_{2}MnSi films on Si(111) or Ge(111) by means of low-temperature molecular beam epitaxy. We find that as-grown Co_{2}MnSi films consist of mixed phases with L2_{1}-ordered structures and microcrystalline ones. As a result, the magnetic moment, which is nearly half of the ideal value, can be obtained even at very low growth temperature. Post-growth annealing was effective to crystallize the microcrystalline phases observed in the as-grown layer, leading to a further enhancement in the magnetic moment. We discuss a difference in growth mechanism between Co_{2}MnSi and other Heusler alloys examined in our previous works.

Wafer-Level Electrical Evaluation of Vertical Carbon Nanotube Bundles as a Function of Growth Temperature

2013-03-21T09:00:00+09:00

Authors: Bart Vereecke, Marleen H. van der Veen, Masahito Sugiura, Yusaku Kashiwagi, Xiaoxing Ke, Daire J. Cott, Thomas Hantschel, Cedric Huyghebaert, and Zsolt Tökei
We have evaluated the resistance of carbon nanotubes (CNTs) grown at a CMOS-compatible temperature using a realistic integration scheme. The structural analysis of the CNTs by transmission electron microscopy (TEM) showed that the degree of graphitization decreased significantly when the growth temperature was decreased from 540 to 400 °C. The CNTs were integrated to form 150-nm-diameter vertical interconnects between a TiN layer and Cu metal trenches on 200 mm full wafers. Wafers with CNTs grown at low temperature were found to have a lower single-contact resistance than those produced at high temperatures. Thickness measurements showed that the low contact resistance is a result of small contact height. This height dependence is masking the impact of CNT graphitization quality on resistance. When benchmarking our results with data from the literature, a relationship between resistivity and growth temperature cannot be found for CNT-based vertical interconnects.

Analytic Compact Model of Ballistic and Quasi-Ballistic Cylindrical Gate-All-Around Metal–Oxide–Semiconductor Field Effect Transistors Including Two Subbands

He Cheng, Shigeyasu Uno, Tatsuhiro Numata, and Kazuo Nakazato — 2013-03-21T09:00:00+09:00

Authors: He Cheng, Shigeyasu Uno, Tatsuhiro Numata, and Kazuo Nakazato
We propose a compact model of drain current in the ballistic and quasi-ballistic modes for cylindrical gate-all-around (GAA)-MOSFETs with two subbands based on the perturbation theory. By setting one unknown parameter, we can use it to express surface potential and electron confinement energy levels to calculate drain current analytically. With our compact model, we obtained a good agreement with the numerical compact model. In addition, we carry out a NMOS inverter circuit simulation using this model.

Impact of Isotope Doping on Phonon Thermal Transport in Silicon Nanowires

Junichi Hattori and Shigeyasu Uno — 2013-03-21T09:00:00+09:00

Authors: Junichi Hattori and Shigeyasu Uno
Phonon transport in silicon nanowires (Si NWs) doped with isotopes is investigated theoretically. The ballistic thermal conductance and diffusive thermal conductivity are calculated at room temperature using the phonon dispersion relations derived through a semiempirical atomistic approach. The thermal conductance and conductivity in ^{28}Si NWs randomly doped with ^{29}Si are smaller than those in the corresponding pure ^{28}Si NW, which can be fully explained by the effect of isotope impurities on the dispersion relations. In [001]-oriented ^{28}Si NWs having a square cross section with a side length of 1.086 nm and randomly doped with ^{29}Si, the maximum reduction in thermal conductivity reaches more than 20%. This reduction leads directly to an improvement in the thermoelectric figure of merit by more than 25%. It is also found that the impact of isotope impurities on phonon transport becomes large with increasing mass difference between the constituent and impurity isotopes or with increasing wire cross-sectional area. Phonon transport in isotopic core–shell Si NWs is also investigated. Some of these Si NWs show increased thermal conductance and conductivity although the increase is very small.

Experimental Study of Two-Terminal Resistive Random Access Memory Realized in Mono- and Multilayer Exfoliated Graphene Nanoribbons

Aya Shindome, Yu Doioka, Nobuyasu Beppu, Shunri Oda, and Ken Uchida — 2013-03-21T09:00:00+09:00

Authors: Aya Shindome, Yu Doioka, Nobuyasu Beppu, Shunri Oda, and Ken Uchida
Two-terminal mono- and multilayer graphene nanoribbon resistive random access memories (ReRAMs) are experimentally demonstrated. Fundamental ReRAM properties, device scalability, and width dependence with device scaling are investigated. The lower switching energy is obtained for smaller channel width, indicating the suitability of graphene nanoribbons for high-density LSIs. Operation mechanism is studied by changing the type of contact metal and the number of graphene layers as well as by performing physical analysis by atomic force microscopy (AFM), cross-sectional transmission electron microscopy (TEM), and electron energy-loss spectroscopy (EELS). Then, it is suggested that the mechanism is the chemical bonding-state change of graphene.

Molecular Dynamics Simulations for Release of Stuck Carbon Nanotube Cantilever Beam toward Nanorelay Application

Atsuko Nagataki, Tatsuya Kagota, Takayuki Arie, and Seiji Akita — 2013-03-21T09:00:00+09:00

Authors: Atsuko Nagataki, Tatsuya Kagota, Takayuki Arie, and Seiji Akita
We have investigated the release of a stuck carbon nanotube cantilever beam by molecular dynamics simulation toward nanorelay applications. We have demonstrated that the successful release of a nanotube arm from the stuck state at room temperature can be realized by the application of a resonant external vibration to the nanotube cantilever beam. The release of the stuck nanotube cantilever beam was well explained by the thermal activation model with a barrier height of the van der Waals interaction between the nanotube arm and the counter electrode.

Energetics and Electronic Structures of Alkanes Adsorbed on Carbon Nanotubes

Katsumasa Kamiya and Susumu Okada — 2013-03-21T09:00:00+09:00

Authors: Katsumasa Kamiya and Susumu Okada
We report on total-energy electronic-structure calculations based on the density functional theory performed on linear alkanes [C_{n}H_{2n+2} with n = 1 to 8] adsorbed on single-walled carbon nanotubes (SWCNTs). We find that all of the alkanes are bound to the SWCNTs. The binding energy of alkane adsorption onto CNT, ΔE(n), is linearly scaled by the length of the alkane chain n: ΔE(n) = -0.048n - 0.038 in units of eV. The electronic structure of alkane–CNT hybrid systems is qualitatively similar to a simple sum of those of an isolated alkane molecule and a pristine CNT. However, detailed analysis of the electronic structure of the hybrid systems reveals that the adsorption of alkane affects the electronic structure of CNTs, depending on the length of the alkane molecule.

First Principles Calculations for Diffusion Barriers of Lithium Intercalation into Graphite with Various Edge Terminations

Takazumi Kawai — 2013-03-21T09:00:00+09:00

Authors: Takazumi Kawai
Lithium atom intercalation into a graphite layer from the step edge to the interlayer region with various edge terminations of graphite is investigated by first-principles electronic structure calculations. The interactions between the step edge and a Li atom depend on the functional group. There is little interaction of the edge with hydrogen termination, while a large interaction traps diffusing Li atoms for termination by oxidative functional groups. The hydroxylic termination would reduce the initial diffusion barrier for the intercalation. Therefore, the controlled edge termination would successfully enhance the charge and discharge properties of Li ion batteries; on the other hand, the progress of oxidative termination would decrease capacity and charge and discharge rates. The diffusion barrier heights of Li is comparable to or larger than those of other rate-limiting factors during charge and discharge, such as desolvation of Li from electrolyte.

Investigation of Cell Structure and Doping for Low-On-Resistance SiC Metal–Oxide–Semiconductor Field-Effect Transistors with Blocking Voltage of 3300 V

2013-03-21T09:00:00+09:00

Authors: Kenji Hamada, Naruhisa Miura, Shiro Hino, Tsuyoshi Kawakami, Masayuki Imaizumi, Hiroaki Sumitani, and Tatsuo Oomori
We have investigated the effect of n-type doping into the junction field-effect transistor region (JFET doping) on the static characteristics of 3300-V-class 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs). The JFET doping technique is significantly effective in reducing the on-resistance of SiC MOSFETs without degradation of the blocking characteristics when the MOS cells are properly designed. The JFET doping reduces the temperature coefficient of the resistance in the JFET region, leading to lower on-resistance of the SiC MOSFETs at high temperatures.

Suppression of Al Memory-Effect on Growing 4H-SiC Epilayers by Hot-Wall Chemical Vapor Deposition

2013-03-21T09:00:00+09:00

Authors: Shiyang Ji, Kazutoshi Kojima, Yuuki Ishida, Sadafumi Yoshida, Hidekazu Tsuchida, and Hajime Okumura
Al memory-effect during the growth of p-type 4H-SiC by hot-wall chemical vapor deposition method was investigated. A technique of suppressing the unintentional Al impurities incorporating into succeeding growth was developed by utilizing “site-competition” growth technology. Lowering C/Si ratio from 1 to 0.4 effectively reduced the level of incorporated Al-impurity almost 3 orders, and a high abrupt Al distribution between Al-doped layer and undoped layer was obtained at a reduction factor about 1/17000 with Al-impurity concentration in the undoped layer decreased to the range of 10^{15} cm^{-3}. In addition, it is found that, due to low C/Si ratio, the nitrogen impurity concentration increases about one order of magnitude up to the order of 10^{16} cm^{-3}. Combining with site-competition growth technology, the influences of growth temperature and pressure on Al-impurity concentration were examined.

Effect of Stacking Faults in Triangular Defects on 4H-SiC Junction Barrier Schottky Diodes

2013-03-21T09:00:00+09:00

Authors: Kazuya Konishi, Shuhei Nakata, Yoshiyuki Nakaki, Yukiyasu Nakao, Akemi Nagae, Takanori Tanaka, Yu Nakamura, Yoshihiko Toyoda, Hiroaki Sumitani, and Tatsuo Oomori
The relationship between stacking faults and the position of the leakage current inside a triangular defect was analyzed. Triangular defects are categorized into two types on the basis of the current–voltage (I–V) characteristics. It was found that stacking faults (SFs) of the 3C structure inside a triangular defect increase leakage current at a reverse bias voltage as well as forward current at a low bias voltage, while SFs of the SF(4,2) structure inside a triangular defect do not lead to deterioration of device performance in this case.

Reduction in Operating Temperature of 25 Series-Connected 820X Concentrator Photovoltaic Module

Yasuyuki Ota, Tsuyoshi Sueto, Hirokazu Nagai, Kenji Araki, and Kensuke Nishioka — 2013-03-21T09:00:00+09:00

Authors: Yasuyuki Ota, Tsuyoshi Sueto, Hirokazu Nagai, Kenji Araki, and Kensuke Nishioka
Under concentration conditions, it is important to manage the operating temperature of a concentrator photovoltaic (CPV) module, because a high-density solar energy enters into the solar cell. We measured the receiver temperature of the CPV module and evaluated the relationship between the temperature and output of the CPV module. 25 series-connected 820X CPV modules with 2- and 4-mm-thick back chassises were fabricated. In the case of a CPV module with a 4-mm-thick back chassis, the receiver temperature was markedly reduced owing to the effective thermal diffusion of the thicker chassis. The absolute conversion efficiency of the CPV module with the 4-mm-thick back chassis was 1.5% higher than that of the module with the 2-mm-thick back chassis. Moreover, we developed a thermal transfer model of the CPV module and calculated the thermal distribution in the CPV module using a thermal transfer simulator.

Post-annealing Effects on Characteristics of Crystalline Germanium Solar Cells with the Double Heterostructure

Tetsuya Kaneko and Michio Kondo — 2013-03-21T09:00:00+09:00

Authors: Tetsuya Kaneko and Michio Kondo
We fabricated crystalline germanium (c-Ge) heterojunction solar cells with a double heterostructure (DH) which consists of hydrogenated amorphous silicon (a-Si:H) layers. In the a-Si:H/c-Ge DH solar cell, the improvement of the conversion efficiency is obtained compared to the c-Ge solar cell having single heterostructure. We investigated effects of post-annealing on characteristics of Ge heterojunction solar cells. The open-circuit voltage (V_{OC}) of Ge heterojunction solar cells increases with increasing post-annealing temperatures above 150 °C. The increase of V_{OC} by post-annealing could be mainly explained by the improvement of passivation quality of a-Si:H for the c-Ge surface. Our results suggest that the a-Si:H double heterostructure is beneficial not only for c-Si-based heterojunction solar cells but also for c-Ge-based heterojunction solar cells.

Analysis of Interfacial Charging Process in Pentacene/C_{60}/Bathocuproine Triple-Layer Organic Solar Cells Using a Maxwell–Wagner Model

Xiangyu Chen, Dai Taguchi, Keanchuan Lee, Takaaki Manaka, and Mitsumasa Iwamoto — 2013-03-21T09:00:00+09:00

Authors: Xiangyu Chen, Dai Taguchi, Keanchuan Lee, Takaaki Manaka, and Mitsumasa Iwamoto
Using the Maxwell–Wagner model, we analyzed the interfacial charging of triple-layer organic solar cells (OSCs). Results showed that the charging processes at the two interfaces depend on each other. The electric-field-induced second-harmonic generation (EFISHG) measurements applying external voltage pulses supported the conclusion. On the other hand, the EFISHG measurements using closed circuits with various external resistances clarified the contribution of interfacial charging to the fill-factor of the OSCs. The dielectric nature of the triple layer of the OSCs governs the working mechanism.

Double Co-deposited Layered Organic Photovoltaic Cells with Sensitivity from Visible to Near-Infrared Regions

Kazuya Yokoyama, Toshihiko Kaji, and Masahiro Hiramoto — 2013-03-21T09:00:00+09:00

Authors: Kazuya Yokoyama, Toshihiko Kaji, and Masahiro Hiramoto
Organic solar cells connecting two photoactive co-deposited layers, i.e., a visible-light-sensitive front layer consisting of metal-free phthalocyanine (H_{2}Pc) and fullerene (C_{60}) and a near-infrared (NIR)-light-sensitive back layer consisting of lead phthalocyanine (PbPc) and C_{60}, were fabricated. The internal quantum efficiency in the visible and NIR regions reached 48 and 43%, respectively. A conversion efficiency of 1.53% was obtained. A model of a function-separated mechanism for the cell, consisting of photocarrier generation by J-PbPc and H_{2}Pc aggregates, hole transport by H-PbPc and H_{2}Pc aggregates, and electron transport by C_{60}, was proposed.

Microstructures and Photovoltaic Properties of Polysilane-Based Solar Cells

2013-03-21T09:00:00+09:00

Authors: Takeo Oku, Junya Nakagawa, Makoto Iwase, Atsushi Kawashima, Kazumi Yoshida, Atsushi Suzuki, Tsuyoshi Akiyama, Katsuhisa Tokumitsu, Masahiro Yamada, and Mika Nakamura
Polysilane-based organic solar cells with bulk heterojunction and heterojunction structures were fabricated by spin-coating using a mixture solution. Microstructures of the solar cells were investigated by X-ray diffraction analysis and transmission electron microscopy, which indicated a nanocomposite and amorphous structure. The effects of phosphorus and boron doping into polysilanes were investigated by electrical measurements, Raman scattering analysis and Hall effect measurements. Here, we discuss the photovoltaic properties and microstructures of the solar cells. Energy levels in the present solar cells are also discussed.

Preparation of Narrow Band-Gap Cu_{2}Sn(S,Se)_{3} and Fabrication of Film by Non-Vacuum Process

Takeshi Nomura, Tsuyoshi Maeda, and Takahiro Wada — 2013-03-21T09:00:00+09:00

Authors: Takeshi Nomura, Tsuyoshi Maeda, and Takahiro Wada
We successfully prepared a Cu_{2}Sn(S_{1-x}Se_{x})_{3} (CTSSe) solid solution with 0≤x≤1.0. CTSSe solid solution powders were synthesized by mixing the elemental powders and post-annealing at 600 °C. The crystal structure of Cu_{2}SnS_{3} (CTS) was characterized by Rietveld refinement of the powder X-ray diffraction data and determined to be a monoclinic crystal system. The band gaps of CTSSe solid solution were determined by the diffuse reflectance spectra of the powder samples and the transmittance spectrum of the film fabricated by a non-vacuum thin-film fabrication process called printing and high-pressure sintering (PHS). The band gap (E_{g}) of CTS is 0.87 eV, which is in good agreement with the recently reported value of monoclinic CTS film. The band gap of the Cu_{2}Sn(S_{1-x}Se_{x})_{3} solid solution linearly decreases from 0.87 eV (x = 0.0) to 0.67 eV (x = 0.6) with increasing Se content. The CTSSe solid solution has potential as a narrow band-gap absorber material for thin-film full spectrum solar cells.

Fabrication and Demonstration of 3-nm-Channel-Length Junctionless Field-Effect Transistors on Silicon-on-Insulator Substrates Using Anisotropic Wet Etching and Lateral Diffusion of Dopants

Shinji Migita, Yukinori Morita, Meishoku Masahara, and Hiroyuki Ota — 2013-02-20T09:00:00+09:00

Authors: Shinji Migita, Yukinori Morita, Meishoku Masahara, and Hiroyuki Ota
Junctionless field-effect transistors (JL-FETs) with a 3 nm channel length are fabricated on silicon-on-insulator (SOI) substrates using simple process techniques. The anisotropic etching of Si crystals by alkaline solution is utilized to form V-grooves and to define nanometer-scale channel structures. Ultrathin channels created on the SOI have a 3 nm channel length that is determined by the edge of V-grooves. Dopants are introduced by ion implantation at the source and drain regions and diffused into the channel region at a high temperature and by long-period annealing. V-groove JL-FETs thus fabricated show superior performances by scaling the thickness of the SOI channel toward 1 nm and less. Through the measurement of many V-groove JL-FETs and a simulation study, it is clarified that the management of channel thickness with atomic-scale precision is indispensable for sub-10 nm FETs.

Improvement of Crystallographic Quality of Electroplated Copper Thin-Film Interconnections for Through-Silicon Vias

2013-02-20T09:00:00+09:00

Authors: Ken Suzuki, Naokazu Murata, Naoki Saito, Ryosuke Furuya, Osamu Asai, and Hideo Miura
The relationship between the electrical properties and crystallographic quality (crystallinity) of electroplated copper thin-film interconnections was investigated. The crystallinity of the grains and grain boundaries of the interconnections was evaluated on the basis of the image quality (IQ) value obtained by electron back-scatter diffraction (EBSD) analysis. The electrical properties of the interconnections vary markedly depending on their crystallinity. The crystallinity also changed markedly as functions of electroplating conditions and the annealing temperature after electroplating. Although the electro migration (EM) resistance of the annealed interconnection was improved, stress-induced migration (SM) was activated by a high residual stress after annealing. To improve electrical reliability without heat treatment after electroplating, the effects of the seed layer under the interconnections on the crystallinity were investigated. As a result, the crystallinity was improved by changing the seed layer from Cu to Ru. In addition, the decrease in current density during electroplating also improved the crystallinity. Therefore, both introducing the Ru seed layer and decreasing the current density during electroplating are effective for developing highly reliable copper interconnections.

Si_{1-y}Ge_{y} or Ge_{1-z}Sn_{z} Source/Drain Stressors on Strained Si_{1-x}Ge_{x}-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

2013-02-20T09:00:00+09:00

Authors: Geert Eneman, An De Keersgieter, Liesbeth Witters, Jerome Mitard, Benjamin Vincent, Andriy Hikavyy, Roger Loo, Naoto Horiguchi, Nadine Collaert, and Aaron Thean
The interaction between two stress techniques, strain-relaxed buffers (SRBs) and epitaxial source/drain stressors, is studied on short, Si_{1-x}Ge_{x}- and Ge-channel planar transistors. This work focuses on the longitudinal channel stress generated by these two techniques. Unlike for unstrained silicon-channel transistors, for strained channels on top of a strain-relaxed buffer a source/drain stressor without recess generates similar longitudinal channel stress than source/drain stressors with a deep recess. The least efficient stress transfer is obtained for source/drain stressors with a small recess that removes only the strained channel, not the substrate underneath. These trends are explained by a trade-off between elastic relaxation of the strained-channel during source/drain recess and the increased stress generation of thicker source/drain stressors. For Ge-channel pFETs, GeSn source/drains and Si_{1-x}Ge_{x} strain-relaxed buffers are efficient stressors for mobility enhancement. The former is more efficient for gate-last schemes than for gate-first, while the stress generated by the SRB is found to be independent of the gate-scheme.

Statistical Analysis of Subthreshold Swing in Fully Depleted Silicon-on-Thin-Buried-Oxide and Bulk Metal–Oxide–Semiconductor Field Effect Transistors

2013-02-20T09:00:00+09:00

Authors: Tomoko Mizutani, Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Hidekazu Oda, Nobuyuki Sugii, and Toshiro Hiramoto
The variability of subthreshold swing (SS) in fully depleted (FD) silicon-on-thin-buried-oxide (SOTB) MOSFETs is statistically analyzed and compared with that of conventional bulk MOSFETs. It is newly found that SS variability is small enough in deep subthreshold region (small drain current I_{ds}) while it increases as increasing I_{ds}. The mechanisms of this behavior is intensively investigated and it is found that the increase in SS variability is caused by current-onset voltage (COV) variability that is due to random dopant fluctuation (RDF). Since SOTB FETs have small COV variability thanks to an intrinsic channel, SS variability is much smaller than bulk FETs, which is a great advantage of FD SOTB in terms of I_{on}/I_{off} ratio.

Self-Heating Effects and Analog Performance Optimization of Fin-Type Field-Effect Transistors

Tsunaki Takahashi, Nobuyasu Beppu, Kunro Chen, Shunri Oda, and Ken Uchida — 2013-02-20T09:00:00+09:00

Authors: Tsunaki Takahashi, Nobuyasu Beppu, Kunro Chen, Shunri Oda, and Ken Uchida
The self-heating effects (SHEs) of bulk and silicon-on-insulator (SOI) fin-type field-effect transistors (FinFETs) and their impacts on circuit performance have been investigated on the basis of a realistic thermal conductivity of silicon. The heat dissipation via interconnect wires and interface thermal resistance in the high-κ gate stack were incorporated in simulations. It is shown that the depth of the shallow trench isolation (STI) of bulk FinFETs cannot be decreased to less than 100 nm owing to the increase in off-state leakage current. We observed that the thermal resistance R_{th} of SOI FinFETs greatly decreases upon thinning the buried oxide (BOX) layer. When the BOX thickness t_{BOX} is less than 50 nm, the R_{th} of SOI FinFETs is smaller than that of bulk FinFETs with an STI thickness of 100 nm, indicating a lower operation temperature of the thin-BOX SOI FinFETs than that of bulk FinFETs. The lower operation temperature of the 5-nm BOX SOI FinFET was confirmed under a practical bias condition for analog operations. In fin width, W_{fin}, versus R_{th} characteristics, a strong W_{fin} dependence of R_{th} was observed only in the bulk FinFETs, implying that fluctuations in W_{fin} result in the variability of the operation temperature of the bulk FinFETs. Analog performance has been analyzed by calculating the cutoff frequency f_{T} and the maximum oscillation frequency f_{max}. We demonstrated that both f_{T} and f_{max} can be maximized in SOI FinFETs by optimizing t_{BOX} with regard to electrical and thermal properties. Better analog performance, and hence the optimization of t_{BOX}, are indispensable for the device design of a FinFET-based system-on-a-chip (SoC) platform.

Compound Semiconductor Tunneling Field-Effect Transistor Based on Ge/GaAs Heterojunction with Tunneling-Boost Layer for High-Performance Operation

2013-02-20T09:00:00+09:00

Authors: Young Jun Yoon, Seongjae Cho, Jae Hwa Seo, In Man Kang, Byung-Gook Park, and Jung-Hee Lee
In this work, a high-performance compound semiconductor tunneling field-effect transistor (TFET) based on germanium (Ge)/gallium arsenide (GaAs) heterojunction with a tunneling-boost layer is investigated. The tunneling-boost layer in the source-side channel alters the energy band-gap structure between the source and the channel, which affects current drivability considerably. It is shown that controlling the lengths of the boosting layer (thin n^{+} GaAs layer) and lightly doped p-type channel (p-GaAs) also has substantial effects on adjusting V_{th} without complications arising from shifting metal workfunction. Furthermore, we evaluate device performances such as on-state current (I_{on}), subthreshold swing (S), intrinsic delay time (τ), and cut-off frequency (f_{T}). The proposed TFET with an n-GaAs length of 12 nm showed an S of 27 mV/dec and approximately 3 times higher I_{on} than that of the device without a boosting layer. Moreover, it is confirmed from the extracted excellent radio-frequency (RF) parameters that the proposed device is suitable for RF applications.

Ion Species Dependence of Relaxation Phenomena of Strained SiGe Layers Formed by Ion-Implantation-Induced Relaxation Technique

Tomohisa Mizuno, Juria Takehi, Youhki Abe, and Hiromu Akamatsu — 2013-02-20T09:00:00+09:00

Authors: Tomohisa Mizuno, Juria Takehi, Youhki Abe, and Hiromu Akamatsu
We have experimentally studied a new H^{+}-ion-induced relaxation technique for compressive-strained SiGe layers on a buried oxide layer (BOX) for high-performance p-channel source heterojunction devices, to improve the crystalline quality of the ion-implanted SiGe layers, using the very steep recoil energy E_{R} distribution of H^{+} ions. In addition, we have compared the H^{+}-ion-induced relaxation phenomena of the strained SiGe with the O^{+}-ion-induced one. We have experimentally shown that the strained SiGe layers can also be fully relaxed even by H^{+} ion implantation, using Raman spectroscopy analysis. In addition, the obtained Raman spectroscopy data show that the crystalline quality of H^{+}-ion-implanted SiGe layers can be improved and is much more uniform, compared with that of the O^{+}-ion-implanted area, as expected. However, high-dose H^{+} ion implantation locally causes the splitting of strained SiGe layers from the BOX layer, which is the technical limitation of H^{+} ions.

A Simple Circuit to Investigate Threshold Voltage Variation and Its Application in Monitoring Negative Bias Temperature Instability Degradation

Jie Hong, Yandong He, Ganggang Zhang, and Xing Zhang — 2013-02-20T09:00:00+09:00

Authors: Jie Hong, Yandong He, Ganggang Zhang, and Xing Zhang
This paper presents a test circuit which can be used to analyze the p-MOSFET threshold voltage (V_{T}) shift and fluctuation. The proposed circuit includes two p-MOSFETs, series connection. Using the circuit, we can directly measure threshold voltage shift on the output side and gather fluctuation statistics of p-MOSFET devices. The principle and the sensitivity of this method are demonstrated, followed by simulation and experimental results. A predictive model of negative bias temperature instability (NBTI) is introduced to analyze the PMOS degradation under constant stress. The NBTI stress experimental results have shown that this circuit can monitor NBTI degradation accurately, and offer a significant improvement in efficiency over existing I_{d}–V_{g} methods.

Characteristics of Lateral Diffused Metal–Oxide–Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide

2013-02-20T09:00:00+09:00

Authors: Chin-Rung Yan, Jone F. Chen, Chung-Yi Lin, Hao-Tang Hsu, Yu-Jie Liao, Min-Ti Yang, Chih-Yuan Chen, Yin-Chia Lin, and Huei-Haurng Chen
Characteristics of lateral diffused metal–oxide–semiconductor (LDMOS) transistors with gradual junction profile by self-alignment implant through dual thicknesses of screen oxide are presented in this letter. Compared with LDMOS transistors with traditional junction profile, this new device shows improved off-state breakdown voltage, less severe in Kirk effect, and wider electrical safe operating area; without sacrificing device drivability. Technology computer aided design (TCAD) simulation results reveal that this new device has smaller electric field both in off- and on-state bias conditions. Hot-carrier induced degradation of this new device under various stress conditions is also investigated and compared with that of the device with traditional junction profile.

Study Trapped Charge Distribution in P-Channel Silicon–Oxide–Nitride–Oxide–Silicon Memory Device Using Dynamic Programming Scheme

2013-02-20T09:00:00+09:00

Authors: Fu-Hai Li, Yung-Yueh Chiu, Yen-Hui Lee, Ru-Wei Chang, Bo-Jun Yang, Wein-Town Sun, Eric Lee, Chao-Wei Kuo, and Riichiro Shirota
In this study, we precisely investigate the charge distribution in SiN layer by dynamic programming of channel hot hole induced hot electron injection (CHHIHE) in p-channel silicon–oxide–nitride–oxide–silicon (SONOS) memory device. In the dynamic programming scheme, gate voltage is increased as a staircase with fixed step amplitude, which can prohibits the injection of holes in SiN layer. Three-dimensional device simulation is calibrated and is compared with the measured programming characteristics. It is found, for the first time, that the hot electron injection point quickly traverses from drain to source side synchronizing to the expansion of charged area in SiN layer. As a result, the injected charges quickly spread over on the almost whole channel area uniformly during a short programming period, which will afford large tolerance against lateral trapped charge diffusion by baking.

Effect of the Active Layer Thickness and Temperature on the Switching Kinetics of GeS_{2}-Based Conductive Bridge Memories

2013-02-20T09:00:00+09:00

Authors: Giorgio Palma, Elisa Vianello, Gabriel Molas, Carlo Cagli, Florian Longnos, Jérémy Guy, Marina Reyboz, Catherine Carabasse, Mathieu Bernard, Faiz Dahmani, Damien Bretegnier, Jacques Liebault, and Barbara De Salvo
In this paper, the effect of the active layer thickness and temperature on the switching kinetics of GeS_{2}-based conductive bridge memories is addressed through electrical characterization. Results are explained in terms of a thermally and field driven ion hopping model for reversible resistance switching. The combined analysis reveals that at high temperature the set voltage and the set resistance decrease. Furthermore, the study suggests that applying the same reset condition, for GeS_{2} thicknesses lower than 50 nm, the conductive filament is almost dissolved, while for thicker layers a portion of the filament still remains.

Switching Model of TaO_{x}-Based Nonpolar Resistive Random Access Memory

Xin Tong, Wenjuan Wu, Zhe Liu, Xuan Anh Tran, Hong Yu Yu, and Yee-Chia Yeo — 2013-02-20T09:00:00+09:00

Authors: Xin Tong, Wenjuan Wu, Zhe Liu, Xuan Anh Tran, Hong Yu Yu, and Yee-Chia Yeo
We report on a novel TaO_{x}-based nonpolar resistive random access memory (RRAM) cell design with a Cr/TaO_{x}/Al (top-to-bottom) structure. Extensive studies of the switching mechanism of the nonpolar RRAM were performed. The thermal coefficient of resistance of the RRAM in the low-resistance state is observed to adopt different polarities depending on how the preceding set operation was performed. On the basis of this observation, the coexistence of metallic ions and oxygen vacancies in the dominant filament is deduced, and a hybrid filament hypothesis is proposed for the first time to explain the observations. A switching model is provided to explain the microscopic changes in the nonpolar TaO_{x}-based RRAM.

A 2.8 µm Pixel-Pitch 55 ke^{-} Full-Well Capacity Global-Shutter Complementary Metal Oxide Semiconductor Image Sensor Using Lateral Overflow Integration Capacitor

Shin Sakai, Yoshiaki Tashiro, Rihito Kuroda, and Shigetoshi Sugawa — 2013-02-20T09:00:00+09:00

Authors: Shin Sakai, Yoshiaki Tashiro, Rihito Kuroda, and Shigetoshi Sugawa
In this paper, a global-shutter complementary metal oxide semiconductor (CMOS) image sensor using lateral overflow integration capacitor (LOFIC) in each pixel without trade-offs between full-well capacity (FWC) and dark current and between FWC and pixel size has been demonstrated. Because the FWC is determined only by LOFIC, a photodiode (PD) and storage diffusion capacitor (SD) are designed focusing on achieving low dark current performance especially. A 2.8 µm pixel pitch Bayer-RGB color CMOS image sensor with the pinned diffusion capacitor for the storage node was fabricated and achieved both 83.3 e^{-}/s at the PD and 58.3 e^{-}/s at the SD dark current at 60 °C and about 55 ke^{-} full well capacity. A high resolution performance, a high FWC performance and a low dark current performance were simultaneously achieved in this image sensor.

A 3 Gbps Non-Contact Inter-Module Link with Twofold Transmission Line Couplers and Low Frequency Compensation Equalizer

2013-02-20T09:00:00+09:00

Authors: Atsutake Kosuge, Tsutomu Takeya, Mitsuru Shioya, Masao Taguchi, and Tadahiro Kuroda
A non-contact inter-module link technique which consists of transmission line couplers (TLCs) and an equalizing receiver is proposed. The non-contact interface allows eliminating metal terminals and eases electro-static discharge (ESD) protection constraints, leading to higher channel bandwidth. Signals pass through two TLCs via a transmission line so that they are differentiated twice (d^{2}v/dt^{2}) and turn into double-peak pulses. To retrieve original waveforms, we developed a low-frequency compensation continuous time linear equalizer (LFC-CTLE) to emphasize the low frequency part converting the double-peak pulses to the first order differentiated shapes, resulting in improving the data rate. To verify this technique, we designed and fabricated a test chip in 0.18 µm CMOS technology and we achieved 3 Gbps data rate at the bit error rate of (BER) less than 10^{-11} with a 10-in. long FR4 micro strip line and two 11 mm length TLCs.

A 3-mW/Gbps 1.8-V Operated Current-Reuse Low-Voltage Differential Signaling Driver Using Vertical Metal–Oxide–Semiconductor Field-Effect Transistors

Satoru Tanoi and Tetsuo Endoh — 2013-02-20T09:00:00+09:00

Authors: Satoru Tanoi and Tetsuo Endoh
A low-voltage differential signaling (LVDS) driver with a new current reuse topology is proposed for low power-supply voltage (V_{DD}) operation. The proposed driver has a new current mirror with shared MOSFET and is designed using vertical MOSFETs. The new current mirror reduces the output degradation to less than half of the conventional. And the design with vertical MOSFETs reduces the voltage drop of the eight-stage cascode circuit to 77.6% of that with planar ones. Our current reuse driver achieves 3-mW/Gbps with 2.5-Gbps and 1.8-V V_{DD} operation in the simulation using 0.18-µm gate length MOSFET parameters. The achieved reduction of the power normalized by the output power at 1.8-V V_{DD} is larger than 30% of that for the conventional drivers.

Effective Mobility Enhancement in Al_{2}O_{3}/InSb/Si Quantum Well Metal Oxide Semiconductor Field Effect Transistors for Thin InSb Channel Layers

2013-02-20T09:00:00+09:00

Authors: Taihei Ito, Azusa Kadoda, Koji Nakayama, Yuichiro Yasui, Masayuki Mori, Koichi Maezawa, Eiji Miyazaki, and Takashi Mizutani
Al_{2}O_{3}/InSb/Si quantum well MOSFETs were fabricated with a thin InSb channel layer grown directly on Si(111) substrates. The InSb thickness ranged from 6 to 25 nm. These thicknesses are close to the critical thickness of InSb on Si, when the InSb layer is grown using a special technique called surface reconstruction controlled epitaxy, which reduces the lattice mismatch from 19.3 to 3.3% by rotating the in-plane InSb axis by 30° with respect to the Si(111) substrate. Good FET characteristics were observed for 10 nm InSb channel devices. The dependence of the device properties on InSb channel thickness was investigated. The enhancement of effective mobility for thin InSb channel devices was demonstrated, which indicates the crystal quality improvement when approaching the critical thickness.

Influence of Metalorganic Vapor Phase Epitaxy Regrowth on Characteristics of InAlN/AlGaN/GaN High Electron Mobility Transistors

2013-02-20T09:00:00+09:00

Authors: Masanobu Hiroki, Noriyuki Watanabe, Narihiko Maeda, Haruki Yokoyama, Kazuhide Kumakura, and Hideki Yamamoto
We fabricated InAlN/AlGaN/GaN heterostructures using a regrowth technique in order to avoid an unintentional Ga incorporation into the InAlN barrier layer. We prepared two types of samples (S1 and S2) using different regrowth sequences: InAlN regrowth on AlGaN/GaN (S1), and InAlN/AlGaN/GaN regrowth on GaN (S2). The characteristics of the high electron mobility transistors (HEMTs) differed depending on the adopted sequence. In current–voltage characteristics, the kinks appear only for the HEMTs using S1 (HEMT-S1). The current reduction induced by gate-bias stress is as large as 20% in HEMT-S1, while it is only 5% in HEMT-S2. Results of our complementary experiments on AlGaN/GaN heterostructures prepared by various regrowth sequences suggest that the inferior device properties of HEMT-S1 can be attributed to higher trap density at the regrowth interfaces. The higher trap density is most likely a result of the AlGaN surface's being more easily oxidized than the GaN surface. Non-uniform decomposition of the AlGaN surface during the heating process prior to the regrowth may also play a role. The fairly a good device performance of HEMT-S2 indicates that InAlN can actually act as a good barrier for GaN-based HEMTs by careful optimization of the fabrication sequence even with a regrowth process.

93–133 GHz Band InP High-Electron-Mobility Transistor Amplifier with Gain-Enhanced Topology

2013-02-20T09:00:00+09:00

Authors: Masaru Sato, Shoichi Shiba, Hiroshi Matsumura, Tsuyoshi Takahashi, Yasuhiro Nakasha, Toshihide Suzuki, and Naoki Hara
In this study, we developed a new type of high-frequency amplifier topology using 75-nm-gate-length InP-based high-electron-mobility transistors (InP HEMTs). To enhance the gain for a wide frequency range, a common-source common-gate hybrid amplifier topology was proposed. A transformer-based balun placed at the input of the amplifier generates differential signals, which are fed to the gate and source terminals of the transistor. The amplified signal is outputted at the drain node. The simulation results show that the hybrid topology exhibits a higher gain from 90 to 140 GHz than that of the conventional common-source or common-gate amplifier. The two-stage amplifier fabricated using the topology exhibits a small signal gain of 12 dB and a 3-dB bandwidth of 40 GHz (93–133 GHz), which is the largest bandwidth and the second highest gain reported among those of published 120-GHz-band amplifiers. In addition, the measured noise figure was 5 dB from 90 to 100 GHz.

Investigation of the Gate Bias Stress Instability in ZnO Thin Film Transistors by Low-Frequency Noise Analysis

2013-02-20T09:00:00+09:00

Authors: Kwang-Seok Jeong, Ho-Jin Yun, Yu-Mi Kim, Seung-Dong Yang, Sang-Youl Lee, Young-Su Kim, Hi-Deok Lee, and Ga-Won Lee
To investigate the electrical instability mechanism under the application of gate bias stress and relaxation, the 1/f noise spectra of two different ZnO thin-film transistors (TFTs) were analyzed. In terms of gate bias dependence (S_{IDS}/I_{DS}), both devices followed a mobility fluctuation model based on the traps in their channel layers prior to and after stress. Device A (channel thickness: 20 nm), recovered its initial noise parameter (α_{app}) after relaxation, in exact agreement with the current–voltage (I–V) measurement results; this shows that in device A, the dominant phenomenon under the application of stress was temporary charge trapping at grain boundary traps. However, in device B (channel thickness: 80 nm), α_{app} did not recover its initial values after relaxation, and transfer parameters, such as V_{TH}, mobility, SS, and N_{t}, degraded after the gate bias stress. Moreover, after the stress, device B showed a reduced gate insulator breakdown voltage. The electrical degradation seen in device B can be explained by trap creation and/or charge injection near channel/gate oxide interfaces, including those within the channel layer.

Electro-Mechanical Q Factor Control of Photonic Crystal Nanobeam Cavity

2013-02-20T09:00:00+09:00

Authors: Ryuichi Ohta, Yasutomo Ota, Hiroyuki Takagi, Naoto Kumagai, Katsuaki Tanabe, Satomi Ishida, Satoshi Iwamoto, and Yasuhiko Arakawa
We design and demonstrate a photonic crystal nanobeam cavity with a Q factor controllable by a micro-electro-mechanical system (MEMS). The cavity is evanescently coupled to an adjacent nanobeam waveguide, and its Q factor is controlled by electro-mechanically adjusting the gap distance between them. We experimentally demonstrate control of the Q factor from 2,250 to 2,750, by applying voltage from 0 to 11 V.

Proposal of Compact Tunable 1×2 Multimode Interference Splitter Based on Multiple Quantum Well

Shintaro Kashima, Joo-Hyong Noh, and Taro Arakawa — 2013-02-20T09:00:00+09:00

Authors: Shintaro Kashima, Joo-Hyong Noh, and Taro Arakawa
We propose a compact tunable 1×2 multimode interference (MMI) splitter based on an InGaAs/InAlAs multiple quantum well for an active trimmer for Mach–Zehnder modulator with a very high extinction ratio. The light power splitting characteristics of the splitter are theoretically investigated by a beam propagation method and a three dimensional finite-difference time-domain method. It is assumed that the core layer is composed of a multiple five-layer asymmetric coupled quantum well (FACQW) that is expected to exhibit a large electrorefractive index change owing to its unique quantum confined Stark effect. By applying reverse voltages and changing slightly the refractive indices of the localized regions surrounded by trenches for electrical isolation, the power splitting ratio can be tuned over a wide range. The length and width of the proposed MMI with four refractive index modulation regions are 192 and 6 µm, respectively. The length can be reduced to 115 µm if the number of index modulation regions is reduced to two, though the tuning range of the splitting ratio is narrowed. The simulation results show that the proposed compact MMI splitter has a low insertion loss and a low power consumption, and is promising for Mach–Zehnder modulators with a very high extinction ratio.

Epitaxial Trilayer Graphene Mechanical Resonators Obtained by Electrochemical Etching Combined with Hydrogen Intercalation

2013-02-20T09:00:00+09:00

Authors: Makoto Takamura, Kazuaki Furukawa, Hajime Okamoto, Shinichi Tanabe, Hiroshi Yamaguchi, and Hiroki Hibino
We report on the mechanical resonance properties of trilayer graphene resonators created by controlling of the layer number. We epitaxially create bilayer graphene and an interfacial buffer layer on a SiC substrate. Using hydrogen intercalation combined with electrochemical etching, we break the Si–C bonds between the buffer layer and SiC substrate surface so that the bilayer graphene and buffer layer turn into three graphene layers. The successful creation of the trilayer graphene resonators is directly observed with a transmission electron microscope. By investigating the frequency shift induced by the laser irradiation, we estimate the thermal expansion coefficient. We find that a quality factor shows a typical temperature dependence of monolayer graphene and carbon-nanotube resonators with a doubly-clamped beam structure. This implies that there exists a general energy loss mechanism for both nanotubes and few-layer-graphene doubly clamped resonators.

Increase of Si_{0.5}Ge_{0.5} Bulk Single Crystal Size as Substrates for Strained Ge Epitaxial Layers

2013-02-20T09:00:00+09:00

Authors: Kyoichi Kinoshita, Osamu Nakatsuka, Yasutomo Arai, Keisuke Taguchi, Hiroshi Tomioka, Ryota Tanaka, and Shinichi Yoda
Compositionally uniform 2 and 10 mm diameter Si_{0.5}Ge_{0.5} bulk crystals have been grown by the traveling liquidus-zone (TLZ) method. The TLZ method requires diffusion controlled mass transport in a melt and crystal size was limited for suppressing convection in a melt. For substrate use, however, larger diameter crystals are required. Increase of crystal diameter was challenged in spite of the concern that compositional homogeneity of grown crystals might be degraded due to faster convective flow in a larger diameter melt. As a result, however, increase of crystal diameter was possible up to 30 mm although single crystal length was limited to 5 mm. Si_{0.55}Ge_{0.45} and Si_{0.6}Ge_{0.4} bulk crystals with 30 mm diameter showed excellent compositional homogeneity and high crystallinity without mosaicity.

Fabrication and Characterization of Metal–Ferroelectric–Insulator–Semiconductor Capacitor Structure with Ferroelectric (Bi,Pr)(Fe,Mn)O_{3} Thin Films

Takeshi Kawae, Yuichiro Seto, and Akiharu Morimoto — 2013-02-20T09:00:00+09:00

Authors: Takeshi Kawae, Yuichiro Seto, and Akiharu Morimoto
(Bi,Pr)(Fe,Mn)O_{3} (BPFM) thin films were deposited on SiO_{2}/Si substrates by a chemical solution deposition method, resulting in the metal–ferroelectric–insulator–semiconductor (MFIS) capacitor structure. Polycrystalline BPFM films were grown on the substrate without impurity phases. Comparing with the capacitance vs voltage (C–V) curves of the MFIS capacitor structures with and without the BPFM self-barrier layer, the BPFM self-barrier layer suppress the formation of charge trap sites in the interface between the BPFM and SiO_{2} layers of the present structure, resulting in the prepared MFIS capacitor structure showing a clockwise C–V hysteresis behavior due to remnant polarization of the BPFM layer. The memory window width in the C–V curve was approximately 0.5 V for the bias voltage sweep from -20 to +20 V.

Direct Heteroepitaxial Growth of ZnO over GaN Crystal in Aqueous Solution

2013-02-20T09:00:00+09:00

Authors: Takahiro Hamada, Akihiro Ito, Nobuaki Nagao, Nobuyasu Suzuki, Eiji Fujii, and Ayumu Tsujimura
We report on the structural and electrical properties of ZnO films grown on surface-treated GaN/Al_{2}O_{3} substrates by chemical bath deposition. X-ray diffraction analysis indicated that the ZnO films had a single-crystalline wurtzite structure with c-axis orientation. The ZnO film exhibited n-type conduction with a carrier concentration of 6.9 ×10^{18} cm^{-3}, an electron mobility of 41 cm^{2}/(V·s), and a resistivity of 2.2 ×10^{-2} Ω·cm. A low specific contact resistivity of 4.3 ×10^{-3} Ω·cm^{2} was obtained at the ZnO/n-GaN interface. Additionally, the ZnO film exhibited high transparency in the visible and infrared region.

Indium-Rich InGaP Nanowires Formed on InP (111)A Substrates by Selective-Area Metal Organic Vapor Phase Epitaxy

Fumiya Ishizaka, Keitaro Ikejiri, Katsuhiro Tomioka, and Takashi Fukui — 2013-02-20T09:00:00+09:00

Authors: Fumiya Ishizaka, Keitaro Ikejiri, Katsuhiro Tomioka, and Takashi Fukui
We studied the growth of indium-rich InGaP nanowires (NWs) on InP (111)A substrates by selective-area metal organic vapor phase epitaxy (SA-MOVPE). We obtained vertically aligned InGaP NWs by optimizing growth conditions, such as group III supply ratio and V/III ratio. We found that the height, diameter, shape, and composition of InGaP NWs depended significantly on the supply ratios of trimethylgallium (TMGa) and trimethylindium (TMIn). As the supply ratio of TMGa was increased, the lateral growth was drastically enhanced, and the uniformity of NWs deteriorated. Furthermore, the sidewall facets of NWs changed from {-211} to {-110} as the supply ratio of TMGa was increased, indicating the possibility of structural transition from wurtzite (WZ) to zinc blende (ZB). We propose a possible growth model for such lateral growth, uniformity, and structural transition. Photoluminescence (PL) measurements revealed that the Ga compositions ranged approximately from 0 to 15%. Our results show that highly uniform InGaP NWs can be grown by controlling the growth conditions.

Optical and Electrical Properties of Au- and Ag-Doped ReSe_{2}

Yu-Ci Jian, Der-Yuh Lin, Jenq-Shinn Wu, and Ying-Sheng Huang — 2013-02-20T09:00:00+09:00

Authors: Yu-Ci Jian, Der-Yuh Lin, Jenq-Shinn Wu, and Ying-Sheng Huang
Single crystals of Au- and Ag-doped ReSe_{2} (ReSe_{2}:Au and ReSe_{2}:Ag) have been grown by chemical vapor transport (CVT) method using iodine as a transporting agent. The optical properties are studied by absorption and polarized-thermoreflectance (PTR) spectroscopy at different polarization angles in the temperature range between 12 and 300 K. The direct band-edge excitonic transitions (E_{1}^{ex}, E_{2}^{ex}, E_{3}^{ex}, and E_{s}^{ex}) have been clearly revealed for the first time in the absorption spectra when the samples are made thin enough. The dominant E_{1}^{ex} and E_{2}^{ex} excitonic transitions gets strongest as the polarization is parallel and perpendicular to the b-axis, respectively. The parameters that describe the temperature dependence of the excitonic transition energy and the broadening function are extracted and discussed. We have also performed electrical conductivity and Hall measurements at different temperatures to derive the activation energy (∼95 and 50 meV for ReSe_{2}:Au and ReSe_{2}:Ag, respectively).

Dual Function of Single Electron Transistor Coupled with Double Quantum Dot: Gating and Charge Sensing

Tomohiro Kambara, Tetsuo Kodera, Yasuhiko Arakawa, and Shunri Oda — 2013-02-20T09:00:00+09:00

Authors: Tomohiro Kambara, Tetsuo Kodera, Yasuhiko Arakawa, and Shunri Oda
We demonstrate gating and charge sensing functions of a lithographically defined single electron transistor (SET). The electrochemical potential of the SET is modulated by applying a voltage to both the source and drain electrodes. The SET integrated with a double quantum dot (DQD) works as a gate electrode for the DQD. Charge transitions in the DQD are detected by the SET through its charge sensing function. This dual function of the SET is useful for saving space in crowded devices with many gates and charge sensors, toward the integration of multiqubits for quantum computation.

Strong Rashba Spin–Orbit Interaction Intensity in Low-Potential-Barrier Quantum Dots

Shiu-Ming Huang, Alexander Olegovich Badrutdinov, Kimitoshi Kono, and Keiji Ono — 2013-02-20T09:00:00+09:00

Authors: Shiu-Ming Huang, Alexander Olegovich Badrutdinov, Kimitoshi Kono, and Keiji Ono
We study the spin splitting energies of different orbital states of quantum dots with a low-potential barrier. The experimental results show that the splitting energies are orbital state dependent. The theoretical analysis is done with a generalization of the Fock–Darwin states in the presence of spin–orbit interactions. The theoretical predictions match well with the experimental observations and exhibits that the Rashba interaction strength in vertical In_{0.05}Ga_{0.95}As/GaAs quantum dots is in the range 80≤λ_{R}≤120 meV Å. This enhanced Rashba spin–orbit interaction intensity can be understood from the high penetration of the electron wavefunction into the quantum well with a low-potential barrier.

Detection of a Charged Two-Level System by Using the Kondo and the Fano–Kondo Effects in Quantum Dots

Tetsufumi Tanamoto, Yu-xi Liu, Xuedong Hu, and Franco Nori — 2013-02-20T09:00:00+09:00

Authors: Tetsufumi Tanamoto, Yu-xi Liu, Xuedong Hu, and Franco Nori
The Kondo effect and the Fano–Kondo effect are important phenomena that have been observed in quantum dots (QDs). We theoretically investigate the transport properties of a coupled QD system in order to study the possibility of detecting a qubit state from the modulation of the conductance peak in the Kondo effect and the dip in the Fano–Kondo effect. We show that the peak and dip of the conductance are both shifted depending on the qubit state. In particular, we find that we can estimate the optimal point and tunneling coupling between the |0> and |1> states of the qubit by measuring the shift of the positions of the conductance peak and dip, as functions of the applied gate voltage on the qubit and the distance between the qubit and the detector.

Printable Top-Gate-Type Polymer Light-Emitting Transistors with Surfaces of Amorphous Fluoropolymer Insulators Modified by Vacuum Ultraviolet Light Treatment

2013-02-20T09:00:00+09:00

Authors: Hirotake Kajii, Daiki Terashima, Yusuke Kusumoto, Ikuya Ikezoe, and Yutaka Ohmori
We investigated the fabrication and electrical and optical properties of top-gate-type polymer light-emitting transistors with the surfaces of amorphous fluoropolymer insulators, CYTOP (Asahi Glass) modified by vacuum ultraviolet light (VUV) treatment. The surface energy of CYTOP, which has a good solution barrier property was increased by VUV irradiation, and the gate electrode was fabricated by solution processing on the CYTOP film using the Ag nano-ink. The influence of VUV irradiation on the optical properties of poly(9,9-dioctylfluorene-co-benzothiadiazole) (F8BT) films with various gate insulators was investigated to clarify the passivation effect of gate insulators. It was found that the poly(methyl methacrylate) (PMMA) film prevented the degradation of the F8BT layer under VUV irradiation because the PMMA film can absorb VUV. The solution-processed F8BT device with multilayer PMMA/CYTOP insulators utilizing a gate electrode fabricated using the Ag nano-ink exhibited both the ambipolar characteristics and yellow-green emission.

Effective Creation of Spin Polarization in p-Type Ge from a Fe/GeO_{2} Tunnel Contact

2013-02-20T09:00:00+09:00

Authors: Aurélie Spiesser, Suguru Watanabe, Hidekazu Saito, Shinji Yuasa, and Koji Ando
We examined electrical creation of spin-polarized carriers in heavily doped p-type Ge from a Fe/GeO_{2} tunnel contact where GeO_{2} is an amorphous insulator. Clear spin accumulation signals were successfully observed up to 300 K down to a very low voltage of 1 mV. In contrast to epitaxial Fe/MgO tunnel contact, the magnitude of spin accumulation signal exhibits a nearly symmetric behavior with respect to the bias voltage polarity. These results establish that GeO_{2} is an effective tunnel barrier for spin injection and detection in germanium.

Room-Temperature Tunneling Magnetoresistance in Magnetic Tunnel Junctions with a D0_{3}-Fe_{3}Si Electrode

2013-02-20T09:00:00+09:00

Authors: Yuichi Fujita, Shinya Yamada, Gotaro Takemoto, Soichiro Oki, Yuya Maeda, Masanobu Miyao, and Kohei Hamaya
To inform room-temperature spin functionality of D0_{3}-ordered Fe_{3}Si, we explore tunneling magnetoresistance (TMR) effects in magnetic tunnel junctions (MTJs) consisting of Co_{60}Fe_{40}/AlO_{x}/Fe_{3}Si on Si. We clearly observe reproducible TMR ratios of ∼20% at room temperature for all MTJs fabricated. By using Julliere's formula, the room-temperature spin polarization (P) value for D0_{3}-ordered Fe_{3}Si can be roughly estimated to be ranging from 0.18 to 0.45 when we assume the P values from 0.5 to 0.2 for Co_{60}Fe_{40}. This study reveals that the room temperature P value for D0_{3}-ordered Fe_{3}Si is relatively small compared with that for Co-based Heusler alloys reported previously.

Analytic Circuit Model of Ballistic Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor for Transient Analysis

2013-02-20T09:00:00+09:00

Authors: Tatsuhiro Numata, Shigeyasu Uno, Yoshinari Kamakura, Nobuya Mori, and Kazuo Nakazato
A fully analytic and explicit model of device properties in the ballistic transport in gate-all-around metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed, which enables circuit simulations. The electrostatic potential distribution in the wire cross section is approximated by a parabolic function. Using the applied potential, the energy levels of electrons are analytically obtained in terms of a single unknown parameter by perturbation theory. Ballistic current is obtained in terms of an unknown parameter using the analytic expression of the electron energy level and the current equation for ballistic transport. We analytically derive the parameter with a one-of-a-kind approximate methodology. With the obtained parameter, the fully analytic and explicit model of device properties such as energy levels, ballistic current, and effective capacitance is derived with satisfactory accuracy compared with the numerical simulation results. Finally, we perform a transient simulation using a circuit simulator, introducing our model to it as a Verilog-A script.

Effects of Trap Levels on Reverse Recovery Surge of Silicon Power Diode

Satoru Machida, Yusuke Yamashita, Tadashi Misumi, and Takahide Sugiyama — 2013-02-20T09:00:00+09:00

Authors: Satoru Machida, Yusuke Yamashita, Tadashi Misumi, and Takahide Sugiyama
In this paper, we report on the effects of trap energy levels on the reverse recovery surge, for the first time. The different current and temperature dependences of the reverse recovery surge with shallow and deep trap energy levels were measured. Results of simulations of current and temperature dependences of the reverse recovery surge with different trap energy levels were similar to measurement results. Through numerical and theoretical analyses based on the Shockley–Read–Hall (SRH) model, it was confirmed that variations in recombination rate due to different trap energy levels affect the current and temperature dependences of the reverse recovery surge. We found that in order to achieve a soft recovery in the design of silicon power diodes, the trap energy levels play a crucial role along with the carrier lifetime profile.

Leakage Current Suppression by Passivation of Defects by Anodic Oxidation of 4H-SiC Schottky Contacts

Masashi Kato, Masaya Kimura, and Masaya Ichimura — 2013-02-20T09:00:00+09:00

Authors: Masashi Kato, Masaya Kimura, and Masaya Ichimura
To suppress the negative influence of defects on 4H-SiC Schottky barrier diode characteristics, we have developed a new method called passivation of defects by anodic oxidation (PDA). This method utilizes anodic oxidation as a means to form oxide films on defects of the 4H-SiC surface, and these oxide films can function as a resistive layer to the leakage current of Schottky barriers. We observed the current–voltage characteristics of Ni Schottky contacts on 4H-SiC before and after PDA. We found that the leakage current was significantly suppressed after PDA, while the increase in series resistance caused by PDA can be negligible when we apply PDA for an optimum time duration. These results suggest that the PDA method is a promising technique to improve the performance of 4H-SiC Schottky barrier diodes.

First-Principles Study of Diffusion of Cu and In Atoms in CuInSe_{2}

Satoshi Nakamura, Tsuyoshi Maeda, and Takahiro Wada — 2013-02-20T09:00:00+09:00

Authors: Satoshi Nakamura, Tsuyoshi Maeda, and Takahiro Wada
Cu and In diffusion in Cu-poor CuInSe_{2} (CIS) with a Cu vacancy have been investigated by first-principles calculations with the generalized gradient approximation. The activation energies and migration pathways are obtained by means of the combination of linear and quadratic synchronous transit (LST/QST) methods and nudged elastic band (NEB) method. The activation energy of Cu migration was 1.06 eV, which is 0.44 eV lower than that of the moving Cu atom located at the center of octahedral site and 0.17 eV lower than that of the moving Cu atom located at center of tetrahedral site. In the transition state, the moving Cu atom is located at the point between the center of the octahedral site and Se atom, which is saddle point of electrostatic potential. The activation energy of In migration (1.70 eV) is much higher than that of Cu migration. The In atom at Cu site (In_{Cu}) in Cu-poor CIS is scarcely to occur at room temperature.

Improvement of Electrical Properties of Silicon Quantum Dot Superlattice Solar Cells with Diffusion Barrier Layers

Shigeru Yamada, Yasuyoshi Kurokawa, Shinsuke Miyajima, and Makoto Konagai — 2013-02-20T09:00:00+09:00

Authors: Shigeru Yamada, Yasuyoshi Kurokawa, Shinsuke Miyajima, and Makoto Konagai
We investigate the effects of a niobium-doped titanium dioxide (TiO_{2}:Nb) diffusion barrier layer on the performance of silicon quantum dot superlattice (Si-QDSL) solar cells. The insertion of a 2-nm-thick TiO_{2}:Nb layer significantly reduces phosphorus diffusion from a highly doped n-type layer into a Si-QDSL layer during thermal annealing at 900 °C. The phosphorous concentration in the Si-QDSL layer of the solar cell with the TiO_{2}:Nb diffusion barrier layer was found to be less than 10^{18} cm^{-3}, which is approximately two orders of magnitude lower than that of the solar cell without the diffusion barrier layer. The reduction in phosphorous concentration leads to the improvement of photo-generated carrier collection in the Si-QDSL layer. The short circuit current density of the solar cell with the diffusion barrier layer was dramatically improved to 1.6 mA/cm^{2} without the degradation of open circuit voltage and fill factor.

Recent articles in Jpn. J. Appl. Phys.

Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory

Interfacial Reaction Mechanisms in Al_{2}O_{3}/Ge Structure by Oxygen Radical Process

Heat-Resistant Co–W Catalytic Metals for Multilayer Graphene Chemical Vapor Deposition

Development of Cu/Insulation Layer Interface Crack Extension Simulation with Crystal Plasticity

Growth of Dense, Vertical and Horizontal Graphene and Its Thermal Properties

High-Current Reliability and Growth Conditions of Multilayer Graphene Wire Obtained by Annealing Sputtered Amorphous Carbon

Sub-Micron-Accuracy Gold-to-Gold Interconnection Flip-Chip Bonding Approach for Electronics–Optics Heterogeneous Integration

Reductant-Assisted Self-Assembly with Cu/Sn Microbump for Three-Dimensional Heterogeneous Integration

Room-Temperature Cu Microjoining with Ultrasonic Bonding of Cone-Shaped Bump

Investigation of Local Bending Stress Effect on Complementary Metal–Oxide–Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

Tunnel Field-Effect Transistor with Epitaxially Grown Tunnel Junction Fabricated by Source/Drain-First and Tunnel-Junction-Last Processes

Impacts of Surface Roughness Reduction in (110) Si Substrates Fabricated by High-Temperature Annealing on Electron Mobility in n-Channel Metal–Oxide–Semiconductor Field-Effect Transistors on (110) Si

Current Enhancement of Green Transistors Compared with Conventional Tunnel Field-Effect Transistors

Influence of Structural Parameters on Electrical Characteristics of Schottky Tunneling Field-Effect Transistor and Its Scalability

Analysis and Modeling of Geometry Dependent Thermal Resistance in Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistors

Novel Field Effect Diode Type Vertical Capacitorless One Transistor Dynamic Random Access Memory Cell with Negative Hold Bit Line Bias Scheme for Improving the Hold Characteristics

Squareness Control in Polarization–Electric Field Hysteresis Curves in Rhombohedral Pb(Zr,Ti)O_{3} Films

Filament Evolution during Set and Reset Transitions in Oxide Resistive Switching Memory

Physical Guiding Principles for High Quality Resistive Random Access Memory Stack with Al_{2}O_{3} Insertion Layer

Forward and Reverse Biasing in Resistive Memories for Fast, Disturb-Free Read, and Verify

Improved Memory Characteristics of A Novel TaN/Al_{2}O_{3}/TiO_{2}/HfO_{2}/SiO_{2}/Si Structured Charge Trapping Memory

Research of Bulk Erase Operation in Vertical Three-Dimensional Cell Array Architecture

A Programmable Difference-of-Gaussian Analog Complementary Metal Oxide Semiconductor Image Sensor Operating in the Subthreshold Regime

False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation

Fractionally Injection-Locked Frequency Multiplication Technique with Multi-Phase Ring Voltage-Controlled Oscillator

Mechanism Study of Gate Leakage Current for AlGaN/GaN High Electron Mobility Transistor Structure Under High Reverse Bias by Thin Surface Barrier Model and Technology Computer Aided Design Simulation

Characterization of Electroluminescence from One-Dimensionally Self-Aligned Si-Based Quantum Dots

Strongly Enhanced Four-Wave Mixing Signal from GaAs/AlAs Cavity with InAs Quantnm Dots Embedded in Strain-Relaxed Barriers

Si Waveguide-Integrated Metal–Semiconductor–Metal and p–i–n-Type Ge Photodiodes Using Si-Capping Layer

Single Photon Generation from an Impurity Center with Well-Defined Emission Energy in GaAs

Complementary Metal Oxide Semiconductor-Compatible Back-Side-Illuminated Photodiode for Optoelectronic Integrated Circuit Devices

Gain Measurement of Highly Stacked InGaAs Quantum Dot Laser with Hakki–Paoli Method

Output Characteristics of a Semiconductor Laser Diode with Double Ring Cavities and a Y-Junction Coupler

Luminescence Properties of Rare-Earth-Doped Thiosilicate Phosphors on Silicon Substrate

Band-Edge Electronic Structure and Pre-existing Defects in Remote Plasma Deposited Non-crystalline SiO_{2} and GeO_{2}

A Comprehensive Study on the Optical Properties of Thin Gold-Doped Rhenium Disulphide Layered Single Crystals

Performance Revelation and Optimization of Gold Nanocrystal for Future Nonvolatile Memory Application

Impact of Illumination on Charge Injection and Accumulation in Organic Transistor in Presence of Plasmonic Nanoparticles

Transparent Organic Thin Film Transistors Using an Oxide/Metal/Oxide Trilayer as Low-Resistance Transparent Source/Drain Electrodes

Synthesis and Physical Vapor Deposition of Low-Molecular-Weight Poly(3,4-ethylenedioxythiophene)

Ultrathin Poly(4-vinylphenol) Interfacial Layer Evaporation for Low-Voltage Operation of Organic Field-Effect Transistors with HfO_{2} Gate Insulator

Fabrication and In vivo Evaluation of Poly(3,4-ethylenedioxythiophene) Stimulus Electrodes for Fully Implantable Retinal Prosthesis

Study of Insertion Characteristics of Si Neural Probe with Sharpened Tip for Minimally Invasive Insertion to Brain

A Wearable Capacitive Sensor for Monitoring Human Respiratory Rate

Detection of Sub-Nano-Tesla Magnetic Field by Integrated Magnetic Tunnel Junctions with Bottom Synthetic Antiferro-Coupled Free Layer

Circuit-Level Model of Phase-Locked Spin-Torque Oscillators

Triggering Mechanism for Neutron Induced Single-Event Burnout in Power Devices

Compact Modeling of Floating-Base Effect in Injection-Enhanced Insulated-Gate Bipolar Transistor Based on Potential Modification by Accumulated Charge

Parasitic Bipolar Effect of a Thin-Film Silicon-on-Insulator Power Metal–Oxide–Semiconductor Field-Effect Transistor at High Temperatures

Plan-View and Cross-Sectional Photoluminescence Imaging Analyses of Threading Dislocations in 4H-SiC Epilayers

Conductivity Degradation of 4H-SiC p–i–n Diode with In-Grown Stacking Faults

Ion Shower Doping Technique for Selective Emitter Structure in Crystalline Silicon Solar Cells

Spectroscopic Detection of Medium Range Order in Device Grade Hydrogenated Amorphous Silicon

Defect Termination of Flash-Lamp-Crystallized Large-Grain Polycrystalline Silicon Films by High-Pressure Water Vapor Annealing

Improvement of Photovoltaic Characteristics by MoO_{3} Doping of Thick Hole-Transporting Films

Incorporation Effect of Silver Nanoparticles on Inverted Type Bulk-Heterojunction Organic Solar Cells

Physical Properties of Amorphous In–Ga–Zn–O Films Deposited at Different Sputtering Pressures

Fabrication of Zinc Oxide Nanopatterns by Quick Gel-Nanoimprint Process toward Optical Switching Devices

Impact of the Hydrogenation Process on the Performance of Self-Aligned Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors

Double-Crystalline Silicon Channel Thin Film Transistors Fabricated Using Continuous-Wave Green Laser for Large Organic Light-Emitting Diode Displays

Depth-Profiling Study on Amorphous Indium–Gallium–Zinc Oxide Thin-Film Transistors by X-ray Photoelectron Spectroscopy

Influence of Oxide Semiconductor Thickness on Thin-Film Transistor Characteristics

Scaling of Coplanar Homojunction Amorphous In–Ga–Zn–O Thin-Film Transistors

Approaches to Decreasing the Processing Temperature for a Solution-Processed InZnO Thin-Film Transistors

Phenylene–Thiophene Oligomer Derivatives for Thin-Film Transistors: Structure and Semiconductor Performances

Performance Enhancement of Top-Contact Pentacene-Based Organic Thin-Film Transistors with Bilayer WO_{3}/Au Electrodes

Thin-Film Transistors Using Uniform and Well-Aligned Single-Walled Carbon Nanotubes Channels by Dielectrophoretic Assembly

Compact Decoder-Type Gate Driver Circuits with Hydrogenated Amorphous Silicon Thin Film Transistors for Active Matrix Displays

Fabrication and Characterization of Flexible Organic Light Emitting Diodes Based on Transparent Flexible Clay Substrates

Highly Conductive Flexible Multi-Walled Carbon Nanotube Sheet Films for Transparent Touch Screen

Reactive Ion Etching Texturing for Multicrystalline Silicon Solar Cells Using a SF_{6}/O_{2}/Cl_{2} Gas Mixture

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

W versus Co–Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes

Quantitative Evaluation of Dopant Concentration in Shallow Silicon p–n Junctions by Tunneling Current Mapping with Multimode Scanning Probe Microscopy

Measurement of Anisotropic Biaxial Stresses in Si_{1-x}Ge_{x}/Si Mesa Structures by Oil-Immersion Raman Spectroscopy

Tensor Evaluation of Anisotropic Stress Relaxation in Mesa-Shaped SiGe Layer on Si Substrate by Electron Back-Scattering Pattern Measurement: Comparison between Raman Measurement and Finite Element Method Simulation

Towards the Integration of Carbon Nanotubes as Vias in Monolithic Three-Dimensional Integrated Circuits

Radio-Frequency Inductors on High-Resistivity Silicon Substrates with a Nanocrystalline Silicon Passivation Layer

Direct Measurement of Carrier Mobility in Intrinsic Channel Tri-Gate Single Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors