Water-Related Hole Traps at Thermally Grown GeO_{2}–Ge Interface

Yusuke Oniki and Tomo Ueno — 2012-04-20T09:00:00+09:00

Authors: Yusuke Oniki and Tomo Ueno
The generation mechanism of positive charge present in germanium oxide film thermally grown on a germanium substrate has been investigated in this study. Water-related hole traps are generated in the interfacial germanium suboxide layer. The negative flat-band voltage shift due to the charged hole traps increases with increasing electric stress field in the oxide. Both low-temperature growth of the oxide film and postmetallization annealing have been proposed for the improvement of the flat-band voltage shift. The former is effective in minimizing the suboxide layer thickness by suppressing germanium monoxide volatilization during the oxide growth. The latter method successfully reduces the density of traps caused by water desorption from the interfacial suboxide layer.

Characteristics of Defect Generation and Breakdown in SiO_{2} for Polycrystalline Silicon Channel Field-Effect Transistor

Izumi Hirano, Masumi Saitoh, Toshinori Numata, and Yuichiro Mitani — 2012-04-20T09:00:00+09:00

Authors: Izumi Hirano, Masumi Saitoh, Toshinori Numata, and Yuichiro Mitani
In this study, the defect generation and breakdown characteristics of a polycrystalline silicon (poly-Si) channel field-effect transistor (FET) have been investigated in detail from the channel area scaling point of view. In the case of a sufficiently larger channel area than the grain size of poly-Si, it was found that defects in SiO_{2} on a poly-Si channel are more easily created than those on a Si(100) channel and a smaller Weibull slope of charge to breakdown (Q_{bd}) for the poly-Si channel than that for the Si(100) channel was observed, resulting in poor reliabilities. When the channel area is reduced to a similar size to that of the grains, the Weibull slope of Q_{bd} for the poly-Si channel FETs becomes steeper and close to that for the Si(100) channel. Grain size control and surface orientation engineering of the poly-Si channel are required to improve the reliability for further scaled poly-Si channel devices.

Experimental and Analytical Characterization of Dual-Gated Germanium Junctionless p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

2012-04-20T09:00:00+09:00

Authors: Dan Dan Zhao, Choong Hyun Lee, Tomonori Nishimura, Kosuke Nagashio, Guo An Cheng, and Akira Toriumi
The operation of germanium (Ge) dual-gated junctionless p-channel field-effect transistors (DG JL pFETs) is demonstrated. The top-gated hole mobility is approximately 120 cm^{2}·V^{-1}·s^{-1}, which is close to the bulk mobility of p-type Ge with a doping concentration of 10^{19} cm^{-3}. The mobility has a weak hole density dependence and increases by applying a negative bottom gate voltage. In addition, simple analytical expressions for both the current–voltage characteristics and the threshold voltage in the linear region of the DG JL pFET are described. The result shows that normally-off Ge DG JL pFETs are achievable. Furthermore, the threshold voltage variation due to the random dopant number fluctuations in the channel is also discussed, which indicates that it can be reduced by decreasing the Ge and oxide thicknesses.

Channel Strain Measurement in 32-nm-Node Complementary Metal–Oxide–Semiconductor Field-Effect Transistor by Raman Spectroscopy

2012-04-20T09:00:00+09:00

Authors: Munehisa Takei, Hiroki Hashiguchi, Takuya Yamaguchi, Daisuke Kosemura, Kohki Nagata, and Atsushi Ogura
We performed a strain analysis of a 32-nm-node microprocessing unit by Raman spectroscopy in conjunction with transmission electron microscopy. The channel surface was exposed by chemical etching and mechanical polishing for Raman spectroscopy. Some defects and Ge concentration variation were observed in embedded SiGe of a p-channel metal–oxide–semiconductor field-effect transistor (pMOSFET). Uniform defects lying at the same angle were observed in the source and drain regions of an n-channel MOSFET (nMOSFET). From the Raman measurement, the Raman peak from strained Si in the pMOSFET shifted toward a higher frequency at approximately 7.5 cm^{-1}, which corresponds to -3.75 GPa (compressive) under the assumption of uniaxial stress along the channel direction. On the other hand, the Raman peak shift from strained Si in the nMOSFET was -1.7 cm^{-1} corresponding to 0.85 GPa (tensile) under the assumption of uniaxial stress. From the nanobeam diffraction measurements, the compressive strain at the channel edge was larger than that at the channel center in the pMOSFET. On the other hand, the tensile strain in the nMOSFET was induced uniformly in the channel region. We think that understanding and control of channel strain introduction are indispensable in the state-of-the-art complementary MOSFET technology.

Experimental Comparisons between Tetrakis(dimethylamino)titanium Precursor-Based Atomic-Layer-Deposited and Physical-Vapor-Deposited Titanium–Nitride Gate for High-Performance Fin-Type Metal–Oxide–Semiconductor Field-Effect Transistors

2012-04-20T09:00:00+09:00

Authors: Tetsuro Hayashida, Kazuhiko Endo, Yongxun Liu, Shin-ichi O’uchi, Takashi Matsukawa, Wataru Mizubayashi, Shinji Migita, Yukinori Morita, Hiroyuki Ota, Hiroki Hashiguchi, Daisuke Kosemura, Takahiro Kamei, Junichi Tsukada, Yuki Ishikawa, Hiromi Yamauchi, Atsushi Ogura, and Meishoku Masahara
In this study, we successfully introduced an atomic-layer-deposited (ALD) titanium nitride (TiN) gate grown with a tetrakis(dimethylamino)titanium (TDMAT) precursor into fin-type metal–oxide–semiconductor field-effect transistor (FinFET) fabrication for the first time, and comparatively investigated the electrical characteristics, including mobility and threshold voltage (V_{th}) variation, of the fabricated ALD and physical-vapor-deposited (PVD)-TiN gate FinFETs. The ALD-TiN gate FinFETs showed superior conformality to the PVD-TiN gate FinFETs. The electron mobilities of the ALD- and PVD-TiN gate FinFETs were comparable in the small L_{g} region. It was also confirmed that the ALD-TiN gate FinFETs showed a smaller V_{th} variation than the PVD-TiN gate FinFETs.

Passivation of Ge(100) and (111) Surfaces by Termination of Nonmetal Elements

DongHun Lee, Kazuki Kubo, Takeshi Kanashima, and Masanori Okuyama — 2012-04-20T09:00:00+09:00

Authors: DongHun Lee, Kazuki Kubo, Takeshi Kanashima, and Masanori Okuyama
The passivation of the Ge surface is an important issue for a high-performance transistor. Therefore, we carried out the theoretical and experimental analyses to search for alternative terminal materials on the Ge surface. First, the chemical reactivities of various nonmetal elements on the Ge surface were simulated by the semi empirical molecular orbital method to passivate the Ge(100) and (111) surface dangling bonds. The simulations showed that F, Cl, and Se are more useful for the treatment of the Ge(100) surface and that F, Cl, S, and Se are more stable on the Ge(111) surface than H. In particular, S is more effective in terminating the dangling bonds by forming a bridge bond (Ge–S–Ge) and more stable on the Ge(111) surface than on the Ge(100) surface. Next, for experimental confirmation, we performed an (NH_{4})_{2}S solution treatment method on the p-type Ge(100) and (111) substrates, and fabricated HfO_{2}/p-Ge metal–insulator–semiconductor (MIS) devices by photo assisted metal organic chemical vapor deposition (MOCVD). As a result, the S-treatment using (NH_{4})_{2}S solution improved more the electrical properties of the HfO_{2}/p-Ge(111) MIS capacitor than those of the capacitor on the Ge(100) substrate. Recently, the sulfur treatment of the Ge surface has been mainly focused on the Ge(100) substrate. However, the results of this study show that the sulfur treatment method using (NH_{4})_{2}S solution is more useful on the Ge(111) surface than on the Ge(100) surface.

Estimation of Breakdown Electric-Field Strength While Reflecting Local Structures of SiO_{2} Gate Dielectrics Using First-Principles Molecular Orbital Calculation Technique

2012-04-20T09:00:00+09:00

Authors: Hiroshi Seki, Yasuhiro Shibuya, Daisuke Kobayashi, Hiroshi Nohira, Kenji Yasuoka, and Kazuyuki Hirose
To achieve metal–oxide–semiconductor field-effect transistors (MOSFETs) with high reliability, it is important to investigate the dielectric breakdown of gate oxide films of MOSFETs. It is known that dielectric breakdown is usually due to the presence of defects in films. Estimating the breakdown electric-field strength while reflecting local structures such as defects is important for investigation of the reliability of gate SiO_{2} films. In this study, we introduce the “recovery rate”, which is a parameter potentially capable of estimating the breakdown electric-field strength while reflecting the local structures of the film. The recovery rate has a strong correlation with the breakdown electric-field strength of bulk Si and Al compounds. Using this correlation, we estimate the breakdown electric-field strength of SiO_{2} with oxygen vacancies and strains.

Fabrication of Graphene Directly on SiO_{2} without Transfer Processes by Annealing Sputtered Amorphous Carbon

2012-04-20T09:00:00+09:00

Authors: Motonobu Sato, Manabu Inukai, Eiji Ikenaga, Takayuki Muro, Shuichi Ogawa, Yuji Takakuwa, Haruhisa Nakano, Akio Kawabata, Mizuhisa Nihei, and Naoki Yokoyama
We fabricated multilayer graphene directly on SiO_{2} by annealing sputtered amorphous carbon with a catalyst – a simple non-chemical vapor deposition method – without the use of complicated transfer processes. Structural analysis revealed that the graphene sheets formed an epitaxial structure aligned to the Co(111) surface between the Co catalyst and SiO_{2} dielectric. In the multilayer graphene, a resistivity of approximately 500 µΩ cm was obtained, which is one order of magnitude higher than that of highly oriented pyrolytic graphite.

Single-Tube Characterization Methodology for Experimental and Analytical Evaluation of Carbon Nanotube Synthesis

2012-04-20T09:00:00+09:00

Authors: Hong-Yu Chen, Albert Lin, Luckshitha Suriyasena Liyanage, Cara Beasley, Nishant Patil, Hai Wei, Subhasish Mitra, and H.-S. Philip Wong
The existing evaluations of the semiconducting/metallic properties of carbon nanotube (CNT) synthesis do not take into account CNT variation and simply characterize the material with only one parameter p_{semi}: the percentage of semiconducting CNTs. Specifically, this p_{semi} figure of merit does not consider intermediate-on–off-ratio CNTs (semiconducting CNTs with poor I_{on}/I_{off}), and yet, such CNTs can have a large impact on device- and circuit-level performance. Inspired by the complementary metal–oxide–semiconductor (CMOS) community, we address this inadequacy by considering intermediate-on–off-ratio CNTs and other CNT variations by offering a holistic view of CNT characterization through parameter distributions. In this paper, a new methodology, called single-tube characterization (STC), is presented, which directly observes and evaluates the distributions of CNT material properties. Such holistic distributions not only enable more accurate characterization and analyses of the material properties and variations, but they also further enable analyses to accurately predict performance and variation at the device- and circuit-levels.

Through Silicon Via Fabrication with Low-κ Dielectric Liner and Its Implications on Parasitic Capacitance and Leakage Current

Lin Zhang, Dau Fatt Lim, Hong Yu Li, Shan Gao, and Chuan Seng Tan — 2012-04-20T09:00:00+09:00

Authors: Lin Zhang, Dau Fatt Lim, Hong Yu Li, Shan Gao, and Chuan Seng Tan
Through silicon via (TSV) has emerged as an essential enabler for three-dimensional integrated circuit (3D IC). The basic TSV structure consisting of a via hole in the Si substrate filled with metal such as copper and lined with a dielectric liner, forms a metal–oxide–silicon (MOS) capacitor structure. To benefit the performance of 3D IC, the TSV used to interconnect vertically stacked dies must introduce small electrical parasitic, such as capacitance. The isolation property of the dielectric liner must also be preserved to control the leakage current. In this work, TSV with acceptable sidewall roughness is achieved and lined with low-κ material with an effective dielectric constant of ∼2.8. Low-κ liner with conformal step coverage is successfully achieved in our fabrication process. Based on electrical measurement, it is found that the integration of the low-κ liner reduces the TSV capacitance by ∼27.6% as compared with the conventional plasma-enhanced tetraethylorthosilicate (PETEOS) oxide liner. In addition, current–voltage (I–V) measurement is carried out to monitor and study the leakage of the low-κ liner. No abrupt breakdown is observed until at least at an electric field of 3 MV/cm which corresponds to 60 V. Annealing of the TSV structure in forming gas (N_{2}/H_{2}) at 350 °C for 30 min successfully reduces the leakage current density by ∼1.6×, to a mid-distribution value of ∼6.8×10^{-6} A/cm^{2}.

Room-Temperature Microjoining of LSI Chips on Poly(ethylene naphthalate) Film Using Mechanical Caulking of Au Cone Bump

Takanori Shuto, Naoya Watanabe, Akihiro Ikeda, and Tanemasa Asano — 2012-04-20T09:00:00+09:00

Authors: Takanori Shuto, Naoya Watanabe, Akihiro Ikeda, and Tanemasa Asano
We show that room-temperature bonding of LSI chips on a resin film made of poly(ethylene naphthalate) (PEN) can be realized by using mechanical caulking of a cone-shaped bump electrode made of Au. A 20-µm-pitch area array of cone-shaped Au bumps was fabricated on a Si wafer by photolithography and electroplating. The counter electrode with cross-shaped slits on the PEN film was composed of a Au (top)/Ni/Al (bottom) layered structure, where Ni and Au layers were deposited by electroless plating on patterned Al. Bonding of about 10,000 bump connections with 184 mΩ/bump has been achieved at room temperature.

Potential Characterization of Interconnect Corrosion by Kelvin Probe and Electrostatic Force Microscopies

Masako Kodera, Yasuhito Yoshimizu, and Kanae Uchida — 2012-04-20T09:00:00+09:00

Authors: Masako Kodera, Yasuhito Yoshimizu, and Kanae Uchida
The fine-scale potential observation was performed by Kelvin probe force microscopy (KFM) and electrostatic force microscopy (EFM) using tungsten interconnects in which the minimum width was 43 nm. It was confirmed that the line connected to pads and/or a transistor has a peculiar KFM potential by comparing it with the surrounding pattern. Only the plugs attached to this line were corroded, while the other plugs remained intact. By comparing the results of KFM and EFM observations, the peculiar potential of the line can be attributed to the electron charge up in the bulk of the sample. Charged electrons induced corrosion not only in the line itself but also in the connected structure. It was also revealed that the particular potential can be suppressed by a wet treatment.

Oxygen-Induced Barrier Failure in Ti-Based Self-Formed and Ta/TaN Barriers for Cu Interconnects

2012-04-20T09:00:00+09:00

Authors: Kazuhiro Ito, Kazuyuki Kohama, Keiji Hamasaka, Yutaka Sonobayashi, Nobuharu Sasaki, Yasuharu Shirai, and Masanori Murakami
To understand the electromigration degradation in Cu interconnects that utilize the TiO_{x} self-formed barrier (SFB) probably due to Cu oxidation at the Cu/barrier interface, Cu films deposited on TiO_{x} SFB and conventional Ta/TaN barriers were annealed in atmospheres of various oxygen concentrations. The Ta layer was preferentially oxidized to give Ta_{2}O_{5}, and contained a large amount of oxygen. The barrier layer, which consisted of Ta_{2}O_{5} and Ta(O), could not suppress Cu diffusion. The TaN layer seemed to remain even after annealing at 400 °C in 10 ppm O_{2}, and still suppressed Cu diffusion. This suggests that the TaN layer plays a key role to suppress barrier failure induced by oxygen originating from pores in dielectrics. On the other hand, the oxygen-induced barrier failure was observed in the TiO_{x} SFB after annealing at 500 °C in 5 ppm O_{2} and more. Oxygen facilitated Cu_{2}O formation above the TiO_{x} SFB, and the Cu_{2}O formation caused discontinuity of the TiO_{x} SFB, leading to the barrier failure. The less oxidized Ti_{2}O_{3} and TiO in the TiO_{x} SFB were not further oxidized to TiO_{2} by oxygen in atmospheres, and thus they would not be oxygen absorbers suppressing the Cu_{2}O formation above the barrier. Thus, for suppressing the Cu_{2}O formation, it is essential to increase oxygen barrier ability of the TiO_{x} SFB (probably increasing Ti concentration of the TiO_{x} SFB).

Mn_{2}O_{3} Slurry Reuse by Circulation Achieving High Constant Removal Rate

2012-04-20T09:00:00+09:00

Authors: Sadahiro Kishii, Ko Nakamura, Kenzo Hanawa, Satoru Watanabe, Yoshihiro Arimoto, Syuhei Kurokawa, and Toshiro K. Doi
Fumed silica is widely used in SiO_{2} chemical mechanical polishing (CMP). In semiconductor processes, only fresh slurry is used, and used slurry is disposed. Sustainable development demands a reduction in waste. Since reuse of slurry is effective for reducing the amount of used slurry generated, we investigated the reuse of Mn_{2}O_{3} slurry and conventional fumed silica slurry. In both cases, abrasive concentration decreases as reuse time increases. The removal rate for Mn_{2}O_{3} slurry maintains a value 4 times that of the conventional fumed silica slurry during slurry reuse, because the removal rate for Mn_{2}O_{3} slurry is almost constant for solid concentrations between 1.0 and 10 wt %. Pad conditioning was not performed for Mn_{2}O_{3} slurry. The removal rate for conventional slurry decreases as the number of times of reuse increases, even when pad conditioning is appropriately performed.

Board-Level Solder Joint Reliability of Edge- and Corner-Bonded Lead-Free Chip Scale Package Assemblies Subjected to Thermal Cycling

Hongbin Shi, Cuihua Tian, and Toshitsugu Ueda — 2012-04-20T09:00:00+09:00

Authors: Hongbin Shi, Cuihua Tian, and Toshitsugu Ueda
In this paper, we present the results of thermal cycling test for edge- and corner-bonded lead-free chip scale packages (CSPs), which was carried out on the basis of the IPC-9701 test standard. Six materials were used in this study: four edge-bond adhesives and two corner-bond adhesives. These adhesives were compared with CSPs with full capillary flow underfill (FCFU) and without adhesives. The thermal cycling test results show that corner-bond adhesive has comparable solder joint reliability performance with CSP without adhesive, and is better than edge-bond adhesive, followed by CSPs with FCFU. In addition, the adhesives with a low coefficient of thermal expansion, a high glass transition temperature and a intermediate storage modulus yielded good performance. Results of detailed failure analysis indicate that the dominant failure mode is solder bulk fatigue cracking near package and/or printed circuit board (PCB) pads, and that the location of critical solder joints change from die edges to package corners with the introduction of adhesives.

Postannealing Effects on Strain/Crystal Quality of Lateral Source Relaxed/Strained Layer Heterostructures Fabricated by O^{+} Ion Implantation

Tomohisa Mizuno, Juria Takehi, and Shou Tanabe — 2012-04-20T09:00:00+09:00

Authors: Tomohisa Mizuno, Juria Takehi, and Shou Tanabe
We have experimentally studied postannealing effects on the relaxation rate of strain and crystal quality of a lateral relaxed/strained heterostructure layer after the O^{+} ion implantation process. We have demonstrated the critical annealing temperature as well as the critical recoil energy E_{R} of implanted O^{+} ions for relaxing the strained layers, using UV-Raman spectroscopy. Moreover, we have shown that the crystal quality increases with increasing postannealing temperature, and high-resolution transmission electron microscopy (HRTEM) images of the cross sections and plane views of the O^{+}-ion-implanted strained-Si layers also show the high crystal quality. Moreover, we have observed a threading dislocation of about 15 nm length between high-quality lateral abrupt-relaxed/strained layer heterostuctures, and the threading dislocation area is a stress buffer layer to form the abrupt lateral-strain distribution.

Recovery Characteristics of Anomalous Stress-Induced Leakage Current of 5.6 nm Oxide Films

2012-04-20T09:00:00+09:00

Authors: Takuya Inatsuka, Yuki Kumagai, Rihito Kuroda, Akinobu Teramoto, Shigetoshi Sugawa, and Tadahiro Ohmi
Anomalous stress-induced leakage current (SILC), which has a much larger current density than average SILC, causes severe bit error in flash memories. To suppress anomalous SILC, detailed evaluations are strongly required. We evaluate the characteristics of anomalous SILC of 5.6 nm oxide films using a fabricated array test pattern, and recovery characteristics are observed. Some characteristics of typical anomalous cells in the time domain are measured, and the recovery characteristics of average and anomalous SILCs are examined. Some of the anomalous cells have random telegraph signals (RTSs) of gate leakage current, which are characterized as discrete and random switching phenomena. The dependence of RTSs on the applied electric field is investigated, and the recovery tendency of anomalous SILC with and without RTSs are also discussed.

Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits

2012-04-20T09:00:00+09:00

Authors: Min-Chul Sun, Sang Wan Kim, Hyun Woo Kim, Garam Kim, Hyungjin Kim, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park
A structure of a tunneling field-effect transistor (TFET) featuring an extremely thin body, a double-gated vertical channel, and a source design to maximize the drive current is proposed and optimized on the basis of technology computer-aided design (TCAD) simulation. The field-coupling effect at the double-gated thin-body channel and an engineered tunneling barrier are implemented to maximize the operation current of the device. Weak current drivability under a small drain bias and the directionality of current flow are the expected challenges in building logic circuits with TFETs. A co-integration scheme to build vertical-channel TFETs and metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed as the solution. A new low-power design using the co-integration scheme is suggested.

Advanced 10 nm Width Silicon-on-Insulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-Insulator Realization Technology

2012-04-20T09:00:00+09:00

Authors: Sung Hwan Kim, Hyun Jun Bae, Chang Woo Oh, Dong-Won Kim, Satoru Yamada, Gyoyoung Jin, and Yonghan Roh
An advanced method of the novel silicon-on-insulator (SOI) realization technology is proposed for the fabrication of SOI tri-gate transistors. Using the new method, 10 nm width SOI tri-gate transistors are successfully fabricated on standard Si bulk wafers, and result in excellent electrical characteristics after optimizing the processing parameters. Among others, low-cost and high manufacturability to fabricate SOI tri-gate transistors are advantages of the proposed method. Formed on the standard Si bulk wafer process, the SOI tri-gate transistors with gate length (L_{G}) of 45 nm have reasonable threshold voltage (V_{TH}) of 0.18 V and showed the enhanced current drivability up to 20%. They also demonstrated good short channel effect immunities: sub-threshold swing (SS) and drain induced barrier lowering (DIBL) were 70 mV/dec and 24 mV/V, respectively. Therefore, the novel method for the novel SOI realization technology proposed in this work will be one of the candidates for the scaling-down strategy in the future.

Nanowire-Width and Dopant-Species Dependences of Carrier Transport Characteristics of Schottky Barrier Source/Drain Nanowire Field-Effect Transistors

2012-04-20T09:00:00+09:00

Authors: Takayuki Ishikawa, Masumi Saitoh, Kensuke Ota, Chika Tanaka, and Toshinori Numata
Schottky barrier (SB) source/drain (S/D) nanowire field-effect transistors (FETs) were fabricated with lateral silicidation process, and their nanowire-width and dopant-species dependences were investigated systematically by means of electrical characterization and physical analyses. Carrier transport characteristics of these nanowire FETs showed a nanowire-width dependence and its dependence varied among dopant species. The degree of the lateral silicidation process also showed nanowire-width and dopant-species dependences. We found that the carrier transport mechanisms depending on S/D dopant species and nanowire width can be attributed to the difference of the lateral silicidation progress.

Advantages of Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors over Planar Ones in Noise Properties

2012-04-20T09:00:00+09:00

Authors: Wei Feng, Ranga Hettiarachchi, Soshi Sato, Kuniyuki Kakushima, Masaaki Niwa, Hiroshi Iwai, Keisaku Yamada, and Kenji Ohmori
We have investigated the low-frequency noise behavior of silicon nanowire metal–oxide–semiconductor field-effect transistors (NWFETs) by comparison with that of a planar FET. We have found that the NWFET exhibits lower noise intensity than the planar FET. By analyzing the factors influential to noise intensity, one of the most possible origins of this advantage of the NWFET results from the electron distribution in the channel in NWFET. Owing to quantum confinement, the position of charge-centroids in the channel of NWFET is located further from the interface, resulting in the lower trapping probability between the electrons and oxide traps. These results clearly demonstrate the advantage of three-dimensional structures in static and noise properties.

Hole Mobility in Accumulation Mode Metal–Oxide–Semiconductor Field-Effect Transistors

Philippe Gaubert, Akinobu Teramoto, Shigetoshi Sugawa, and Tadahiro Ohmi — 2012-04-20T09:00:00+09:00

Authors: Philippe Gaubert, Akinobu Teramoto, Shigetoshi Sugawa, and Tadahiro Ohmi
The paper deals with the investigation of the mobility in accumulation mode p-channel metal–oxide–semiconductor field-effect transistors (p-MOSFETs). The mobility extracted following the conventional methodology used for the inversion mode p-MOSFETs is actually incorporating a component related to the silicon-on-insulator (SOI) layer. Thus, a very simple and efficient technique to remove the contribution coming from the SOI layer has been proposed. This ultimately led to the extraction of the hole mobility of the accumulation layer. Its study carried out for several doping concentrations revealed a universal behavior similar to the one of the inversion layer. To finish, the contribution of the SOI layer to the measured mobility has been done and revealed a linear trend with the doping concentration. As a result, a simple and very efficient modeling of the mobility in the accumulation mode p-MOSFETs, incorporating the contribution of both the channel and bulk regions, has been achieved.

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

Yiming Li and Hui-Wen Cheng — 2012-04-20T09:00:00+09:00

Authors: Yiming Li and Hui-Wen Cheng
This work estimates electrical and transfer-characteristic fluctuations in 16-nm-gate high-κ/metal gate (HKMG) metal–oxide–semiconductor field effect transistor (MOSFET) devices and inverter circuit induced by random interface traps (ITs) at high-κ/silicon interface. Randomly generated devices with two-dimensional (2D) ITs at HfO_{2}/Si interface are incorporated into quantum-mechanically corrected 3D device simulation. Device characteristics, as influenced by different degrees of fluctuation, are discussed in relation to random ITs near source and drain ends. Owing to a decreasing penetration of electric field from drain to source, the drain induced barrier lowering (DIBL) of the edvice decreases when the number of ITs increases. In contrast to random-dopant fluctuation, the screening effect of device's inversion layer cannot effectively screen potential's variation; thus, devices still have noticeable fluctuation of gate capacitance (C_{G}) under high gate bias. The cutoff frequency decreases as increasing the number of ITs owing to the decreasing transconductance and increasing C_{G}. Decreasing on-state current and increasing C_{G} further result in increasing intrinsic gate delay time (τ) when the number of ITs increases. The fluctuation magnitude of DIBL, cutoff frequency, and τ above is increased as the number of ITs increases. Even for cases with the same number of random ITs, noise margins (NMs) of the 16-nm-gate complementary metal–oxide–semiconductor inverter circuit are still quite different due to the different distribution of random ITs. The NMs of inverter circuit increase as the number of random ITs increases; however, the NMs' fluctuations are increased due to the more sources of fluctuation at HfO_{2}/Si interface of HKMG devices.

64 kbit Ferroelectric-Gate-Transistor-Integrated NAND Flash Memory with 7.5 V Program and Long Data Retention

Xizhen Zhang, Mitsue Takahashi, Ken Takeuchi, and Shigeki Sakai — 2012-04-20T09:00:00+09:00

Authors: Xizhen Zhang, Mitsue Takahashi, Ken Takeuchi, and Shigeki Sakai
A 64 kbit (kb) one-transistor-type ferroelectric memory array was fabricated and characterized. Pt/SrBi_{2}Ta_{2}O_{9}/Hf–Al–O/Si ferroelectric-gate field-effect transistors (FeFETs) were used as the memory cells. The gate length and width were 5 and 5 µm, respectively. The array design was based on NAND flash memory organized as 8 word lines × 32 blocks × 256 bit lines. Erase, program, and nondestructive-read operations were demonstrated in every block. Threshold-voltage (V_{th}) reading of all the 64 kb memory cells showed a clear separation between their all-erased and all-programmed states. A checkerboard pattern was also programmed in a block and the two distinguishable V_{th} distributions were read out. The V_{th} retention of a block of 2 kb memory cells showed no significant degradation after two days.

Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell

Kousuke Miyaji, Yasuhiro Shinozuka, and Ken Takeuchi — 2012-04-20T09:00:00+09:00

Authors: Kousuke Miyaji, Yasuhiro Shinozuka, and Ken Takeuchi
This paper proposes for the first time the completely complemental metal–oxide–semiconductor (CMOS) compatible embedded flash memory with the small cell size as well as the lowest process cost. The single transistor cell with the minimum channel length and width realizes the ideal smallest cell. The non-volatile memory operation is realized with locally injected electrons at the drain-edge by the hot electron injection. This paper also proposes the novel forward-bias assisted erase. The proposed memory is experimentally demonstrated with the 65 nm standard CMOS process without additional process or mask. The cell size is 10F^{2} with the 65 nm CMOS logic design rule. The excellent reliability such as 100-times program/erase endurance, 10-year data retention and high immunity to the read/program/erase disturb is also experimentally demonstrated. The proposed cell is the ideal candidate for the code-storage embedded non-volatile memories in system-on-chip and microcontroller unit.

Fabrication of Floating-Gate-Type Fin-Channel Double- and Tri-Gate Flash Memories and Comparative Study of Their Electrical Characteristics

2012-04-20T09:00:00+09:00

Authors: Yongxun Liu, Takahiro Kamei, Takashi Matsukawa, Kazuhiko Endo, Shinichi O’uchi, Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa, Tetsuro Hayashida, Kunihiro Sakamoto, Atsushi Ogura, and Meishoku Masahara
Floating-gate (FG)-type fin-channel double-gate (DG) and tri-gate (TG) flash memories with different control-gate (CG) lengths (L_{CG}) from 76 to 256 nm have successfully been fabricated by using (110)-oriented silicon on insulator (SOI) wafers, and their electrical characteristics have been comparatively investigated. It was experimentally found that better short channel effect (SCE) immunity, smaller threshold voltage (V_{t}) variations, and a higher program speed are obtained in the TG-type flash memories than in the DG-type memories. The higher performance of the TG-type flash memory is partly due to the additional top gate and recessed buried oxide (BOX) region, which strengthen the controllability of the channel potential and increase the coupling ratio of the FG to CG. Moreover, it was also found that the measured source–drain (SD) breakdown voltage (BV_{DS}) is higher than 3.2 V even when L_{CG} was reduced to 76 nm. Therefore, the developed fin-channel TG structure is expected to be very useful for the fabrication of scaled NOR-type flash memory.

Re-Examination of Performance and Reliability Degradation in Metal–Oxide–Nitride–Oxide–Semiconductor Memory with Ultrathin SiN Charge Trap Layers

2012-04-20T09:00:00+09:00

Authors: Haruka Kusai, Misako Morota, Masato Oda, Shosuke Fujii, Kiwamu Sakuma, and Masato Koyama
We demonstrated that the degradation of program characteristics in metal–oxide–nitride–oxide–semiconductor (MONOS) devices consisting of an ultrathin (∼2 nm) SiN charge trap layer is due to a decrease in the electron capture efficiency, instead of a reduction in the number of available trap sites. From the data retention properties with applied gate bias voltage, we clarified that charge loss through the tunnel layer during data retention becomes more significant with decreasing SiN thickness. These results indicate that to improve the performance and reliability of MONOS devices with an ultrathin SiN charge trap layer, measures must be taken to enhance the capture cross section of the traps and to inhibit carrier motion in the SiN layer simultaneously.

Robust Data Retention and Superior Endurance of Silicon–Oxide–Nitride–Oxide–Silicon-Type Nonvolatile Memory with NH_{3}-Plasma-Treated and Pd-Nanocrystal-Embedded Charge Storage Layer

Sheng-Hsien Liu, Wen-Luh Yang, Yu-Ping Hsiao, and Tien-Sheng Chao — 2012-04-20T09:00:00+09:00

Authors: Sheng-Hsien Liu, Wen-Luh Yang, Yu-Ping Hsiao, and Tien-Sheng Chao
In this study, we investigated an ammonia (NH_{3}) plasma-pretreatment (PT) for suppressing the formation of interface states between metal nanocrystals (NCs) and the surrounding dielectric during the NC forming process with the aim of obtaining a highly reliable Pd NC memory. The discharge-based multipulse (DMP) technique was performed to analyze the distribution of trap energy levels in the Pd NCs/Si_{3}N_{4}-stacked storage layer. Through DMP analysis, it is confirmed that the NH_{3} PT not only significantly increases the quality of the surrounding dielectric of metal NCs but also effectively passivates shallow trap sites in the Si_{3}N_{4} trapping layer. As compared with the sample without NH_{3} PT, the NH_{3}-plasma-treated device exhibits better reliability characteristics such as excellent charge retention (only 5% charge loss for 10^{4} s retention time) and very high endurance (no memory window narrowing after 10^{5} program/erase cycles). In addition, the robust multilevel cell retention properties of the NH_{3}-plasma-treated memory are also demonstrated.

Improvement of Uniformity of Resistive Switching Parameters by Selecting the Electroformation Polarity in IrO_{x}/TaO_{x}/WO_{x}/W Structure

2012-04-20T09:00:00+09:00

Authors: Amit Prakash, Siddheswar Maikap, Chao Sung Lai, Heng Yuan Lee, W. S. Chen, Frederick T. Chen, Ming Jer Kao, and Ming Jinn Tsai
A route to improve the uniformity of key resistive switching memory parameters such as SET/RESET voltages, low/high-resistance states as well as switching cycles is demonstrated in an IrO_{x}/TaO_{x}/WO_{x}/W simple resistive memory stack by selecting the electroformation polarity. The various stack layers are confirmed by high-resolution transmission electron microscopy, energy dispersive X-ray spectroscopy, and X-ray photoelectron spectroscopy analyses. Cumulative probability plots of the key memory parameters show tight distribution. The oxygen vacancy filaments are formed/ruptured owing to polarity-dependent oxygen ion migration, which is the switching mechanism in the TaO_{x}/WO_{x} bilayers, and improved resistive switching parameters under positive formation polarity are observed. The fabricated device has shown good potential for multilevel capability with a low voltage operation of ±3 V. The device has shown an excellent read endurance of >10^{5} cycles and data retention up to 10 years at 85 °C.

Reset Current Reduction with Excellent Filament Controllability by Using Area Minimized and Field Enhanced Unipolar Resistive Random Access Memory Structure

2012-04-20T09:00:00+09:00

Authors: Kyung-Chang Ryoo, Jeong-Hoon Oh, Sunghun Jung, Hongsik Jeong, and Byung-Gook Park
We firstly propose a novel resistive random access memory (RRAM) cell structure, which makes it possible to minimize the switching area and to maximize the electrical field where resistive switching occurs, resulting in the improvement of resistive switching characteristics. With excellent structural advantages, resistive switching characteristics such as reset current and set voltage fluctuation are improved through the enhancement of conductive filament (CF) controllability. A simple fabrication process is delivered and the device performance from the viewpoints of the forming voltage, set voltage, and reset current is investigated. Conducting defect effects are also investigated in comparison with the conventional RRAM cell structure. Numerical simulation is performed using a random circuit breaker (RCB) model to confirm the proposed structure.

Complementary Metal Oxide Semiconductor Compatible Hf-Based Resistive Random Access Memory with Ultralow Switching Current/Power

2012-04-20T09:00:00+09:00

Authors: Feifei Zhang, Xiang Li, Bin Gao, Bing Chen, Peng Huang, Yihan Fu, Yuansha Chen, Lifeng Liu, Jinfeng Kang, Navab Singh, Lo Guo-Qiang, and Dim-Lee Kwong
Although Resistive random access memory (RRAM) is a promising alternative for next-generation nonvolatile memory, it still suffers from high switching current/power, resulting in large selectors that are normally in series with resistive devices. In this paper, a novel Dynamic random access memory (DRAM) like one-transistor–one-resistor (1T1R) structure is proposed, in which the source/drain of the transistor also serves as the bottom electrode of the RRAM device. Complementary metal oxide semiconductor (CMOS) compatible Hf-based Si/HfO_{2}/TiN RRAM devices were fabricated and ultralow switching current/power was obtained. The set/reset current can be as low as 50 nA/1.25 nA. The programming power for set and reset is only 18 µW and 1.625 nW, respectively. The mechanism of both Schottky emission and electronic hopping via oxygen vacancy defects is proposed to explain the measured resistive switching characteristics.

Flexible One Diode–One Resistor Crossbar Resistive-Switching Memory

2012-04-20T09:00:00+09:00

Authors: Jiun-Jia Huang, Tuo-Hung Hou, Chung-Wei Hsu, Yi-Ming Tseng, Wen-Hsiung Chang, Wen-Yueh Jang, and Chen-Hsi Lin
We report the first demonstration of a flexible one diode–one resistor (1D1R) resistive-switching (RS) memory cell capable of high-density crossbar array implementation at an extremely low cost. A Ti/TiO_{2}/Pt diode with a large rectifying ratio and a stable Ni/HfO_{2}/Pt unipolar RS memory element have been fabricated on a polyimide substrate using only room-temperature processes. No significant degradation of the rectifying ratio of the TiO_{2} diode and the cycling variations, retention, and read disturb immunity of the HfO_{2} memory was observed in the bending state. The series 1D1R cell shows highly reproducible unipolar RS because of the low reset current of the HfO_{2} memory, which greatly mitigates the adverse effect of diode series resistance. Furthermore, the 1D1R cell can effectively suppress read interference and realize a crossbar array as large as 512 kbit.

Excellent Uniformity and Multilevel Operation in Formation-Free Low Power Resistive Switching Memory Using IrO_{x}/AlO_{x}/W Cross-Point

Writam Banerjee, Sk. Ziaur Rahaman, and Siddheswar Maikap — 2012-04-20T09:00:00+09:00

Authors: Writam Banerjee, Sk. Ziaur Rahaman, and Siddheswar Maikap
Excellent uniformity and multilevel operation in formation-free low-power resistive switching memory fabricated using the IrO_{x}/AlO_{x}/W cross-point structure have been investigated. The thickness of the deposited films has been measured by high-resolution transmission electron microscopy with energy dispersive X-ray spectroscopy for each layer. The cross-point resistive switching memory devices have a tight distribution of SET/RESET voltages and low/high-resistance states as well as switching cycles. A high resistance ratio of >8×10^{2} is obtained. This memory device shows excellent AC endurance of >5×10^{3} cycles, read endurance of >1×10^{5} cycles, and 10-year-data retention at 85 °C at a low power of 55 µW and low-current compliances of 50–200 µA. This study is not only important for cross-point memories but will also help in the design of high-density nanoscale nonvolatile memories in the future.

Record Resistance Ratio and Bipolar/Unipolar Resistive Switching Characteristics of Memory Device Using Germanium Oxide Solid Electrolyte

2012-04-20T09:00:00+09:00

Authors: Sheikh Ziaur Rahaman, Siddheswar Maikap, Samit Kumar Ray, Heng-Yuan Lee, Wei-Su Chen, Frederick T. Chen, Ming-Jer Kao, and Ming-Jinn Tsai
The bipolar and unipolar resistive switching characteristics of a memory device using a Cu filament in a new Cu/GeO_{x}/W structure under low-voltage operation (<1.5 V) have been investigated. The germanium oxide (GeO_{x}) solid electrolyte with a thickness of approximately 12 nm has been observed by both high-resolution transmission electron microscopy (HRTEM) and energy-dispersive X-ray spectroscopy analyses. A small device size of 150×150 nm^{2} has been observed by HRTEM. The composition of Ge:O has been investigated by X-ray photoelectron spectroscopy analysis. The memory device shows bipolar switching under current compliances of 1 nA–50 µA with a large SET voltage of approximately 0.5 V and unipolar switching with a larger current compliance of >100 µA. This memory device has excellent uniformity in SET/RESET voltages, low resistance state/high resistance state (LRS/HRS), long read endurance of >1×10^{5} cycles, and good data retention of >1×10^{4} s with high resistance ratios of >10^{5} in the bipolar mode and >10^{9} in the unipolar mode.

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

Kousuke Miyaji, Chinglin Hung, and Ken Takeuchi — 2012-04-20T09:00:00+09:00

Authors: Kousuke Miyaji, Chinglin Hung, and Ken Takeuchi
The scaling trends and limitation in sub-20 nm a bulk and silicon-on-insulator (SOI) NAND flash memory is studied by the three-dimensional (3D) device simulation focusing on short channel effects (SCE), channel boost leakage and channel voltage boosting characteristics during the program-inhibit operation. Although increasing punch-through stopper doping concentration is effective for suppressing SCE in bulk NAND cells, the generation of junction leakage becomes serious. On the other hand, SCE can be suppressed by thinning the buried oxide (BOX) in SOI NAND cells. However, the boosted channel voltage decreases by the higher BOX capacitance. It is concluded that the scaling limitation is dominated by the junction leakage and channel boosting capability for bulk and SOI NAND flash cells, respectively, and the scaling limit is decreased to 9 nm using SOI NAND flash memory cells from 13 nm in bulk NAND flash memory cells.

Electrical Property of DNA Field-Effect Transistor: Charge Retention Property

2012-04-20T09:00:00+09:00

Authors: Naoto Matsuo, Shyogo Takagi, Kazushige Yamana, Akira Heya, Tadao Takada, and Shin Yokoyama
We discovered the charge retention property of the field-effect transistor (FET) in a Si gate/SiO_{2}/DNA channel structure. The DNA FET with the Si source and drain showed hole conduction, and the drain current was controlled by the gate voltage application. In addition, the experimental results that currents similar to the space change limited currents (SCLCs) and hysteresis were observed in the drain current–drain voltage (I_{d}–V_{d}) characteristics indicate that the negative charges captured at the trap sites in the DNA enhance the hole currents. Also, the drain currents increased as the repetition number of the measurement increased. However, by inserting the refresh process of gate voltage application of -50 V between each measurement, the current increase was restrained. This phenomenon indicates that the trap and detrap process of electrons occurs in the DNA channel depending on the gate voltage application. The charge retention mechanism was also discussed.

Areal and Structural Effects on Oxide-Based Resistive Random Access Memory Cell for Improving Resistive Switching Characteristics

2012-04-20T09:00:00+09:00

Authors: Kyung-Chang Ryoo, Jeong-Hoon Oh, Sunghun Jung, Hongsik Jeong, and Byung-Gook Park
A new technical improvement in understanding the resistive switching characteristics of unipolar resistive random access memory (RRAM) is investigated. It is possible to minimize reset current (I_{RESET}), set voltage variation, and forming voltage (V_{FORMING}), which results in a wide sensing margin and high density applications by using a conducting filament (CF) minimized structure up to a 10 nm technology node. Its structural advantages enable I_{RESET} to be tuned with excellent manufacturability. Numerical simulation is also performed using a random circuit breaker (RCB) model, showing that the proposed structure elucidates the resistive switching improvement.

Evaluation of the WO_{x} Film Properties for Resistive Random Access Memory Application

2012-04-20T09:00:00+09:00

Authors: Yi-Yueh Chen, Wei-Chih Chien, Ming-Hsiu Lee, Yi-Chou Chen, Alfred T. H. Chuang, Tian-Jue Hong, Su-Jien Lin, Tai-Bor Wu, and Chih-Yuan Lu
The formation condition, microstructure, and growth kinetics of the WO_{x} layer for WO_{x} resistive random access memory are investigated. To understand the optimal condition for the rapid thermal oxidation process which forms the WO_{x} layer, various annealing temperature and annealing time are systemically studied through transmission electron microscopy, X-ray diffraction, Raman spectra analyses and electrical characterizations. The growth kinetics for WO_{x} under rapid thermal oxidation is found similar to the one for thermal oxidation on silicon. The electrical forming voltages of the WO_{x} cells are also found independent from the oxide thickness, which further suggests the switching behavior of WO_{x} resistive random access memory takes place at the interface but not the bulk.

Effect of Oxidation Amount on Gradual Switching Behavior in Reset Transition of Al/TiO_{2}-Based Resistive Switching Memory and Its Mechanism for Multilevel Cell Operation

Jeong-Hoon Oh, Kyung-Chang Ryoo, Sunghun Jung, Yongjik Park, and Byung-Gook Park — 2012-04-20T09:00:00+09:00

Authors: Jeong-Hoon Oh, Kyung-Chang Ryoo, Sunghun Jung, Yongjik Park, and Byung-Gook Park
To analyze and explain the gradual reset switching property of the bipolar switching resistive random access memory (RRAM) for multilevel cell (MLC) operation, the effect of the amount of plasma oxidation on the gradual reset switching behavior of the Al/TiO_{2}-based RRAM cell structure is investigated. The device that undergoes plasma oxidation in a shorter time has a better ON/OFF current (I_{ON}/I_{OFF}) ratio and shows increased ON current (I_{ON}). The device that undergoes long plasma oxidation occasionally shows the step reset switching behavior because of the thick conductive filament formation in the ON state. This is clearly explained by the different conduction mechanisms during the ON state.

Formation-Polarity-Dependent Improved Resistive Switching Memory Performance Using IrO_{x}/GdO_{x}/WO_{x}/W Structure

2012-04-20T09:00:00+09:00

Authors: Debanjan Jana, Siddheswar Maikap, Ta Chang Tien, Heng Yuan Lee, Wei-Su Chen, Frederick T. Chen, Ming-Jer Kao, and Ming-Jinn Tsai
The formation-polarity-dependent improved resistive switching memory performance using a new IrO_{x}/GdO_{x}/WO_{x}/W structure has been investigated. The memory device has been observed by both high-resolution transmission electron microscopy and energy dispersive X-ray spectroscopy. The thicknesses of the GdO_{x} and WO_{x} layers are observed to be approximately 15 and 5.5 nm, respectively. All layers are also analyzed by X-ray photoelectron spectroscopy. The resistive switching mechanism is filament formation/rupture in the high-κ GdO_{x} layer, which is controlled by the oxygen ion migration in bilayer GdO_{x}/WO_{x} films under negative and positive formation polarities. Excellent uniformity of SET/RESET voltages, low/high resistance states, and switching cycles have been observed under positive formation polarity owing to the charge trapping/detrapping in the high-κ GdO_{x} switching layer. The memory device shows a long endurance of >10^{4} times, and extrapolated 10-year data retention at 85 °C. This device shows great potential for future nonvolatile memory (NVM) applications.

Manipulation of Dispersed Magnetic Beads for On-Chip Immunoassay

Tomohiro Ishikawa, Jaesung Lee, and Ryo Miyake — 2012-04-20T09:00:00+09:00

Authors: Tomohiro Ishikawa, Jaesung Lee, and Ryo Miyake
To provide a simple and low-cost mobile immunoassay platform, a test chip on which dispersed magnetic beads are manipulated was designed and fabricated by a 180 nm standard complementary metal–oxide–semiconductor (CMOS) process. In preliminary experiments, beads that have a diameter of 2.8 µm were successfully manipulated and their motion were captured and analyzed. Then, an immunoassay was conducted on the chip. First, the nonspecific binding of hydrophilic beads coated with an antibody was compared with that of hydrophobic beads that were used for the preliminary experiments. Next, comparison of an immunoassay of mouse IgG with a control assay and a test on the feasibility of the blocking process were conducted simultaneously. The beads coated with the antibody were successfully immobilized onto the chip surface in the presence of the target antigen, which was checked through bead manipulation. This indicates that an immunoassay on an inexpensive CMOS chip is feasible using an affordable amount of driving current.

Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing

Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, and Hidetoshi Onodera — 2012-04-20T09:00:00+09:00

Authors: Takashi Matsumoto, Hiroaki Makino, Kazutoshi Kobayashi, and Hidetoshi Onodera
We propose a multicore large-scale integration (LSI) lifetime extension method, which is based on negative bias temperature instability (NBTI) recovery-based self-healing and circuit parallelization. NBTI recovery is characterized by the recently proposed NBTI sensor with 400 ns measurement delay that measures the off-leak current of p-channel metal–oxide–semiconductor (PMOS) transistors. The circuit is fabricated in a commercial 65 nm complementary MOS (CMOS) technology. It is found that the recoverable component of the LSI performance characterized by the off-leak current remains almost constant after repeatedly adding NBTI stress. The NBTI stress corresponds to circuit operation for several years at room temperature and a nominal operating voltage. It is also found that the amount of NBTI recovery can be tuned by the relaxation time in a real application, and it follows log t from 400 ns to 3000 s. It is shown that for multicore LSI, by recovering one of the n + 1 cores, the n-core LSI system does not stop and the lifetime can be extended by NBTI recovery. For the first time, transforming silicon area into LSI reliability is shown to be a promising and realistic concept for the ever-shrinking CMOS technology.

Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal–Oxide–Semiconductor Technology Including Its Distance Dependences

2012-04-20T09:00:00+09:00

Authors: Tania Ansari, Wataru Imafuku, Masahiro Yasuda, Hans Jürgen Mattausch, and Tetsushi Koide
As the very large scale integration (VLSI) circuits move deeper into the range of sub-100 µm processes due to the continued scaling efforts, designers increasingly face the variations of design parameters as major roadblocks. These variations include the deviation of process, voltage, and temperature values from the nominal specifications and are of paramount concern as they result in a deviation of the performance of ICs from the originally intended design. Thus, variations reduce the yield of the chip production and increase design cost and the design timing schedule. In this paper, we are presenting location-based within-die variation trends in 65 nm technology across the die, which are derived from measured delays of adjustable ring oscillators. The measured data of the test chips in a 65 nm complementary metal–oxide–semiconductor (CMOS) technology indicate that the magnitude of the position based relative variation is 3–7 times larger than for 180 nm technology. At low voltage (0.7 V), this relative variation is significantly increased (>3 times) in comparison to the variation at nominal supply voltage.

0.1 V 13 GHz Transformer-Based Quadrature Voltage-Controlled Oscillator with a Capacitor Coupling Technique in 90 nm Complementary Metal Oxide Semiconductor

2012-04-20T09:00:00+09:00

Authors: Tatsuya Kamimura, Sang-yeop Lee, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu
A low power-supply voltage and high-frequency quadrature voltage-controlled oscillator (QVCO) using a combination of capacitor coupling and transformer feedback techniques is presented. The capacitor coupling technique can boost the transconductance of the LC-VCO core and coupling transconductance of QVCO at high frequency. Also, this technique can improve the quality factor of the QVCO at high frequency with low power-supply voltage, compared with the conventional QVCO. In addition, the capacitor coupling QVCO with transformer feedback can improve the quality factor of QVCO. Using this topology, the QVCO is able to operate at over 10 GHz with lower power-supply voltage. Implemented in the 90 nm complementary metal oxide semiconductor (CMOS) process, the proposed QVCO measures 1-MHz-offset phase noise of -94 dBc/Hz at 13 GHz while consuming 0.68 mW from a 0.1 V power-supply.

High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme

2012-04-20T09:00:00+09:00

Authors: Seiryu Sasaki, Masahiro Yasuda, Akio Kawabata, Tetsushi Koide, and Hans Jürgen Mattausch
A compact multi-bit encoding concept for nearest-distance search-speed improvement of scalable and reliable associative-memories utilizing a mapping operation of the distances into frequency space is reported. The distance differences are transformed into signal delays which are finally detected with a time-domain winner-take-all (WTA) circuit. Ring oscillators programmable in discrete frequency steps are used for the distance–frequency mapping. This implementation enables to decrease the effects of process-induced variations, because the step size is a constraint-free design parameter. To further improve the search reliability, frequency dividers are used to enlarge the size of the frequency steps. The multi-bit encoder achieves a substantial search-time reduction by optimizing the basic-ring oscillator delay for distance zero with a path-selecting scheme. The proposed multi-bit encoding concept has been evaluated with two test-chip designs in 180 nm complementary metal oxide semiconductor (CMOS) technology. Search-time reductions by a factor 1.7 in typical search cases and a compact circuit implementation are verified.

Postfabrication Independent Inductance and Quality Factor Adjustments of On-Chip Inductors by Above-CMOS Processing for Rapid Prototyping of Radio Frequency System on Chips

Yuki Sasaki and Koji Kotani — 2012-04-20T09:00:00+09:00

Authors: Yuki Sasaki and Koji Kotani
The flexible adjustment of on-chip inductor characteristics after a regular complementary metal–oxide–semiconductor (CMOS) fabrication was realized by the “above-CMOS” processing technology for radio frequency (RF) system-on-a-chip (SoC) rapid prototyping. It is shown that the above-CMOS metal pattern formation in a chip-by-chip manner can both increase and decrease the inductance (L) values of on-chip inductors. It is realized by applying various planar patterns of a metal layer deposited on the passivation layer of the chip. To increase the modification range of the characteristics and to establish an independent L and quality factor (Q) adjustment scheme, we have newly developed a pre-design method and a Q-compensation method. By combining these methods, the effective L and Q values of the on-chip inductors can be independently and arbitrarily modified. The adjustment of the input impedance matching frequency of a low-noise amplifier (LNA) using this scheme has also been demonstrated.

An Inverter-Based Wideband Low-Noise Amplifier in 40 nm Complementary Metal Oxide Semiconductor

2012-04-20T09:00:00+09:00

Authors: Dayang Nur Salmi Dharmiza, Mototada Oturu, Satoru Tanoi, Hiroyuki Ito, Noboru Ishihara, and Kazuya Masu
Multistandard RF chips have been highly demanded for multipurpose wireless applications. However, in RF circuits, a low-noise amplifier (LNA) plays an important role in determining the receiver's performance. In this paper, we present a scalable wideband LNA based on complementary metal oxide semiconductor (CMOS) inverters, employing two bandwidth expansion techniques to achieve a large bandwidth without using inductors. Fabricated by the 40 nm CMOS process, the LNA attains 0.1–8.0 GHz of flat bandwidth with S_{21}=17.5 dB and S_{11}≤-10 dB. The minimum NF measured is 5.1 dB and the power consumption is 14.3 mW at 1.3 V. The LNA core circuit is as small as 0.001 mm^{2} since no large passive device is used. A study of LNA scalability has been conducted by comparing the performances of circuits with the same topology fabricated by the 65, 90, and 180 nm CMOS processes.

Wireless Charge Based Capacitance Measurement Circuits with On-Chip Spiral Inductor for Radio Frequency Identification Biosensor

Boram Kim, Shigeyasu Uno, and Kazuo Nakazato — 2012-04-20T09:00:00+09:00

Authors: Boram Kim, Shigeyasu Uno, and Kazuo Nakazato
A wireless measuring system of charge based capacitance measurement (CBCM) circuit has been designed and demonstrated for biomedical applications. The radio frequency identification (RFID) chip that includes on-chip spiral inductor tag antenna, and RFID circuit, and CBCM sensor chip are fabricated within standard complementary metal oxide semiconductor (CMOS) process. The capacitance change caused by DNA detection can be converted into the voltage output using capacitance-to-voltage conversion circuit. To confirm the transmission of the capacitance, the poly-capacitor of fixed capacitance and on-chip spiral inductor tag antenna were fabricated using 1.2 µm, 2-metal, 2-poly CMOS technology. As a result of measurement, three different capacitances (34, 141, 564 fF) were detected wirelessly.

An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television

2012-04-20T09:00:00+09:00

Authors: Sang-Kug Han, Hoon Choi, Kyo-Ho Moon, Young-Seok Choi, Kyung-Deuk Jeong, Kwang-Mook Park, and Sie-Young Choi
We have developed the integrated amorphous silicon gate driver circuit using the model extraction technique of the inverted staggered and nonsymmetric amorphous silicon (a-Si) thin film transistor. The relation between capacitance characteristics of hydrogenated a-Si (a-Si:H) integrated transistors and the output signal of the gate driver circuit is analyzed using UTMOST IV ver. 1.6.4.R and SMARTSPICE ver. 3.19.15.C. The accuracy of the simulated gate output signal using voltage-controlled capacitance modeling is verified with measured data. The a-Si gate driver circuit using the proposed (TFT) model increased the accuracy of rising (95.3%) and falling (92%) time, compared to the conventional model. The suggested model extraction technique can be used for bottom gate and asymmetric TFT structures.

Fully Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian Generation Circuits

Renyuan Zhang and Tadashi Shibata — 2012-04-20T09:00:00+09:00

Authors: Renyuan Zhang and Tadashi Shibata
An analog support vector machine (SVM) processor employing a fully parallel self-learning circuitry was developed for the classification of highly dimensional patterns. To implement a highly dimensional Gaussian function, which is the most powerful kernel function in classification algorithms but computationally expensive, a compact analog Gaussian generation circuit was developed. By employing this proposed Gaussian generation circuit, a fully parallel self-learning processor based on an SVM algorithm was built for 64 dimension pattern classification. The chip real estate occupied by the processor is very small. The object images from two classes were converted into 64 dimension vectors using the algorithm developed in a previous work and fed into the processor. The learning process autonomously proceeded without any clock-based control and self-converged within a single clock cycle of the system (at 10 MHz). Some test object images were used to verify the learning performance. According to the circuit simulation results, it was shown that all the test images were classified into correct classes in real time. A proof-of-concept chip was designed in a 0.18 µm complementary metal–oxide–semiconductor (CMOS) technology, and the performance of the proposed SVM processor was confirmed from the measurement results of the fabricated chips.

A Wide-Range Tunable Level-Keeper Using Vertical Metal–Oxide–Semiconductor Field-Effect Transistors for Current-Reuse Systems

Satoru Tanoi and Tetsuo Endoh — 2012-04-20T09:00:00+09:00

Authors: Satoru Tanoi and Tetsuo Endoh
A wide-range tunable level-keeper using vertical metal–oxide–semiconductor field-effect transistors (MOSFETs) is proposed for current-reuse analog systems. The design keys for widening tunable range of the operation are a two-path feed-back and a vertical MOSFET with back-bias-effect free. The proposed circuit with the vertical MOSFETs shows the 1.23-V tunable-range of the input level with the 2.4-V internal-supply voltage (V_{DD}) in the simulation. This tunable-range of the proposed circuit is 4.7 times wider than that of the conventional. The achieved current efficiency of the proposed level-keeper is 66% at the 1.2-V output with the 2.4-V V_{DD}. This efficiency of the proposed circuit is twice higher than that of the traditional voltage down converter.

Low-Turn-on-Voltage Heterojunction Bipolar Transistors with a C-Doped InGaAsSb Base Grown by Metalorganic Chemical Vapor Deposition

Takuya Hoshi, Hiroki Sugiyama, Haruki Yokoyama, Kenji Kurishima, and Minoru Ida — 2012-04-20T09:00:00+09:00

Authors: Takuya Hoshi, Hiroki Sugiyama, Haruki Yokoyama, Kenji Kurishima, and Minoru Ida
We demonstrate the low-turn-on-voltage InP-based heterojunction bipolar transistors (HBTs) with a C-doped InGaAsSb base grown by metalorganic chemical vapor deposition. As the solid In content of InGaAsSb increases, not only the near-band-edge emission peak energy in photoluminescence spectra of the InGaAsSb film but also the turn-on base–emitter voltage of the HBT with an InGaAsSb base decrease. These results are attributed to the reduction of the InGaAsSb band gap with the increase of solid In content. We obtain the turn-on voltage of 0.35 V at collector current density of 1 A/cm^{2} in the HBT with a In_{0.22}Ga_{0.78}As_{0.73}Sb_{0.27} base, which is one of the lowest turn-on voltages ever reported.

Schottky Source/Drain InAlN/GaN Metal–Insulator–Semiconductor High-Electron-Mobility Transistor with High Breakdown Voltage and Low On-Resistance

Qi Zhou, Hongwei Chen, Chunhua Zhou, Zhihong Feng, Shujun Cai, and Kevin J. Chen — 2012-04-20T09:00:00+09:00

Authors: Qi Zhou, Hongwei Chen, Chunhua Zhou, Zhihong Feng, Shujun Cai, and Kevin J. Chen
In this work, we present a novel device technology of using Schottky source/drain (SSD) in InAlN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) for off-state breakdown voltage V_{BD} improvement. The Schottky source/drain design can effectively prevent the source carrier injection compared to the conventional MISHEMTs, leading to enhanced V_{BD} in the SSD MISHEMTs. A V_{BD} of 460 V is obtained in an InAlN/GaN SSD MISHEMTs with low specific R_{on} of 2.27 mΩ·cm^{2}, at a 170% V_{BD} improvement compared to conventional MISHEMTs. Despite the Schottky source/drain used, a SSD MISHEMT with a gate length of 1 µm exhibits respectable drain current density of 416 mA/mm and transconductance of 113 mS/mm.

High Integrity SiO_{2} Gate Insulator Formed by Microwave-Excited Plasma Enhanced Chemical Vapor Deposition for AlGaN/GaN Hybrid Metal–Oxide–Semiconductor Heterojunction Field-Effect Transistor on Si Substrate

2012-04-20T09:00:00+09:00

Authors: Hiroshi Kambayashi, Takehiko Nomura, Sadahiro Kato, Hirokazu Ueda, Akinobu Teramoto, Shigetoshi Sugawa, and Tadahiro Ohmi
High quality SiO_{2} gate insulator has been demonstrated for GaN metal–oxide–semiconductor (MOS) transistor which has high performance with normally-off operation. The SiO_{2} films formed on GaN by microwave-excited plasma enhanced chemical vapor deposition (MW-PECVD) and annealed after deposition exhibits a low-interface state density between SiO_{2} and GaN, a high-breakdown field, and a high charge-to-breakdown. The SiO_{2} films have been also applied to the gate insulator of AlGaN/GaN hybrid MOS heterojunction field-effect transistor (HFET) on Si substrate. The MOS-HFET show excellent properties with the threshold voltage of 4.2 V and the maximum field-effect mobility of 161 cm^{2} V^{-1} s^{-1}.

Deep levels in n-GaN Doped with Carbon Studied by Deep Level and Minority Carrier Transient Spectroscopies

Unhi Honda, Yujiro Yamada, Yutaka Tokuda, and Kenji Shiojima — 2012-04-20T09:00:00+09:00

Authors: Unhi Honda, Yujiro Yamada, Yutaka Tokuda, and Kenji Shiojima
Electron and hole traps in the carbon doping of n-type GaN films grown by metal–organic chemical vapor deposition were investigated by deep level and minority carrier transient spectroscopies. Four electron traps were observed in the samples. Of these traps, the electron trap concentration of E2 (E_{c}-0.40 eV) rose with increasing C incorporation. Two hole traps H1 (E_{v} + 0.86 eV) and H2 also showed the dependence of C doping concentration. According to these results, traps E2, H1, and H2 correspond to C-related defects. Moreover, the energy level of H1 was consistent with an ionization energy of 0.9 eV of C_{N} acting as a deep acceptor, which might give rise to conventional yellow luminescence and current collapse of GaN-based high electron mobility transistors (HEMTs). This was confirmed by photoluminescence (PL) spectra that the integrated intensity of yellow luminescence (YL) band was largely dependent on C incorporation. Therefore, we speculated that hole trap H1 might be responsible for a broad YL band in the samples.

Impact of Data Transmission over 10 Gbps on High-Density and Low-Cost Optoelectronic Module with Polynorbornene Waveguides

2012-04-20T09:00:00+09:00

Authors: Yuka Ito, Shinsuke Terada, Shinya Arai, Makoto Fujiwara, Tetsuya Mori, Koji Choki, Takafumi Fukushima, and Mitsumasa Koyanagi
We proposed a rigid/flex optoelectronic (O/E) module with 48-channel polymeric waveguides for short-distance board-level optical interconnection. A flexible O/E test module was fabricated in the following two steps by using standard packaging processes. First, two vertical cavity surface emitting laser diodes (VCSELs) and one VCSEL driver (VD) were flip-chip bonded to a completed flexible printed circuit board (PCB), and two photodiodes (PDs) and one transimpedance amplifier/limiting amplifier (TIA/LA) to another flexible PCB. Second, the two flexible PCBs were attached with a polynorbornene (PNB) sheet in which high-density PNB waveguides were formed by UV exposure. Active areas of VCSELs and PDs on the flexible PCBs were aligned to micromirrors of the waveguides with -6 µm offset toward the signal propagation direction. We successfully demonstrated data transmission over 10 Gbps and low inter-channel crosstalk of less than -20 dB was achieved in the flexible O/E test module with 120-mm-long and 62.5-µm-pitch waveguides.

Large Area of Ultraviolet GaN-Based Photonic Quasicrystal Laser

2012-04-20T09:00:00+09:00

Authors: Cheng-Chang Chen, Ching-Hsueh Chiu, Po-Min Tu, Ming-Yen Kuo, M. H. Shih, Ji-Kai Huang, Hao-Chung Kuo, Hsiao-Wen Zan, and Chun-Yen Chang
In this study, large-area GaN-based photonic quasicrystal (PQC) nanopillars were fabricated on an n-GaN substrate using the nanoimprint lithography (NIL) technique. Under optical pumping condition, a high lasing action from the GaN photonic quasicrystals was observed. The lasing wavelength is at 366 nm with a low threshold power density of 0.009 kW/cm^{2}. To confirm the band-edge lasing mode, the finite-element method (FEM) was used to perform the simulation for the 12-fold symmetry photonic quasicrystal lattices.

Femtosecond Laser-Excited Two-Photon Fluorescence Microscopy of Surface Plasmon Polariton

2012-04-20T09:00:00+09:00

Authors: Tatsumi Hattori, Atsushi Kubo, Katsuya Oguri, Hidetoshi Nakano, and Hideki T. Miyazaki
We demonstrate microscopic imaging of surface plasmon polaritons (SPPs) on silver films excited by 11 fs near-infrared laser pulses. A fluorescence layer placed on the silver film converts surface electromagnetic fields to propagating lights in visible wavelengths via two-photon excitation process. The wavelength of SPP determined from fluorescence micrographs agrees well with the calculated value of SPP at the silver-fluorescent film interface.

Analysis of Phase Matching Conditions for Generating Second Harmonic in ZnO Channel Waveguides

Yuta Taira, Tomohiro Kita, Edgar Yoshio Morales Teraoka, and Hirohito Yamada — 2012-04-20T09:00:00+09:00

Authors: Yuta Taira, Tomohiro Kita, Edgar Yoshio Morales Teraoka, and Hirohito Yamada
We describe a phase-matching scheme for generating the second harmonic in ZnO channel waveguides using a modal phase-matching (MPM) method. We found that MPM can be achieved between the TM_{00} mode of the fundamental wave and the TM_{02} mode of the second-harmonic wave by using structural dispersion of the waveguide mode. Furthermore, we calculated the normalized conversion efficiency by taking the overlap integral of each waveguide mode and the effective area of the fundamental wave into account, and obtained a sufficiently high conversion efficiency. These results show that ZnO channel waveguides are very attractive for generating second-harmonic devices.

Terahertz Radiation from a (113)B GaAs/AlAs Coupled Multilayer Cavity Generated by Ultrashort Laser Pulse Excitation

2012-04-20T09:00:00+09:00

Authors: Sho Katoh, Toshikazu Takimoto, Yoshinori Nakagawa, Ken Morita, Takahiro Kitada, and Toshiro Isu
Terahertz (THz) radiation was demonstrated using a GaAs/AlAs coupled multilayer cavity grown on a (113)B GaAs substrate. Two cavity modes realized in the high-reflection band were simultaneously excited using ultrashort laser pulses for the difference frequency generation (DFG). Oscillations with a period of 0.3 ps were clearly observed in the temporal waveforms of time-resolved THz measurements. The oscillation period well agreed with the difference frequency between the two cavity modes (3.3 THz). We also measured the THz waveforms depending on the polarization direction of the excitation laser pulses, and the anisotropic signal amplitudes also agreed with the calculated anisotropy of the second-order nonlinear polarization on the (113)B GaAs substrate.

GaAs/AlAs Multilayer Cavity with Er-Doped InAs Quantum Dots Embedded in Strain-Relaxed InGaAs Barriers for Ultrafast All-Optical Switches

2012-04-20T09:00:00+09:00

Authors: Hyuga Ueyama, Tomoya Takahashi, Yoshinori Nakagawa, Ken Morita, Takahiro Kitada, and Toshiro Isu
Er-doped InAs quantum dots (QDs) embedded in strain-relaxed InGaAs barriers, which exhibit an extremely short carrier decay time of 3 ps due to the nonradiative process, are superior materials for ultrafast all-optical switches using a GaAs/AlAs multilayer cavity. The intensity of the nonlinear signal due to the absorption saturation in the 20-layer stack of the Er-doped QDs was increased by increasing the In composition in the strain-relaxed InGaAs barriers while keeping the extremely short decay time. The QD cavity structure, which consisted of GaAs/AlAs distributed Bragg reflector (DBR) multilayers and a half-wavelength cavity layer containing two layers of the Er-doped QDs was grown by molecular beam epitaxy. The transmission change signal was clearly observed in the time-resolved measurements at the cavity mode wavelength of 1.55 µm. The response time of 4 ps was observed for the Er-doped QD cavity, which was much shorter than that (12 ps) for the undoped QD cavity.

Silicon Ring Optical Modulator with p/n Junctions Arranged along Waveguide for Low-Voltage Operation

Yoshiteru Amemiya, Ryuichi Furutani, Masataka Fukuyama, and Shin Yokoyama — 2012-04-20T09:00:00+09:00

Authors: Yoshiteru Amemiya, Ryuichi Furutani, Masataka Fukuyama, and Shin Yokoyama
For low-voltage and high-speed operation, a Si ring optical modulator, where p/n junctions are arranged along the waveguide of the ring resonator, is proposed. In this device, a switching speed of over 30 GHz and a modulation of 3 dB are estimated at a low operation voltage of 1 V by simulation. Optimum design parameters are obtained: the carrier concentration is 1×10^{18} cm^{-3} and the length of the p- and n-type regions is 0.4 µm. The modulators were fabricated and the performance was evaluated. The modulation is 1.25 dB at 6 V, which is lower than the simulated value. This is explained by the unexpected low carrier concentration. It is suggested that the optimization of the fabrication process will yield better performance.

Electroluminescence from One-Dimensionally Self-Aligned Si-Based Quantum Dots with High Areal Dot Density

Katsunori Makihara, Hidenori Deki, Mitsuhisa Ikeda, and Seiichi Miyazaki — 2012-04-20T09:00:00+09:00

Authors: Katsunori Makihara, Hidenori Deki, Mitsuhisa Ikeda, and Seiichi Miyazaki
Self-aligned Si-based quantum dots (QDs) with an areal density as high as ∼10^{13} cm^{-2} have been successfully fabricated on GeH_{4}-adsorbed ultrathin SiO_{2} by the process sequence consisting of Si-QDs formation by controlling low-pressure chemical vapor deposition (LPCVD) using pure Si_{2}H_{6}, selective Ge-LPCVD from 5% GeH_{4} diluted with He, thermal oxidation of the dots, thermal desorption of Ge oxide, and subsequent formation of the Si-QDs. In semitransparent Au-gate diodes with self-aligned dots so-prepared, when carriers were injected to the self-aligned Si-QDs from the n-Si(100) substrate for electrons and from the Au top electrode for holes, electroluminescence (EL) in the near-infrared region at room temperature becomes observable with an increase in current at positive biases over a threshold voltage as low as ∼1.2 V at the Au top electrode. Note that, in the case of an areal dot density of ∼10^{13} cm^{-2}, the EL threshold voltage was reduced down to ∼60% of that of ∼10^{11} cm^{-2} and emission intensity was enhanced markedly by a factor of ∼425 in comparison with the case of ∼10^{11} cm^{-2} under the same current density. This is clear evidence of not only an increase in radiative recombination rate in the self-aligned structure but also an improvement of recombination efficiency due to a decrease in current leakage with increasing dot density.

Light Detection and Emission in Germanium-on-Insulator Diodes

2012-04-20T09:00:00+09:00

Authors: Kazuki Tani, Shin-ichi Saito, Yong Lee, Katsuya Oda, Toshiyuki Mine, Toshiki Sugawara, and Tatemi Ido
We fabricated a germanium-on-insulator (GeOI) lateral p–i–n diode by a standard silicon process and characterized it as a photodetector and a light emitter. For the photodetector, we observed photosensitivity by an excitation light with the wavelength of 1550 nm. The experimental radio frequency response has completely agreed with simulated results, and the observed 3-dB bandwidth of 2 GHz was limited by contact resistances. For the light emitter, the electroluminescence spectra have broad peaks located at 1460 nm, much shorter than that of photoluminescence spectra located at 1600 nm. The difference was presumably attributable to the poor interface properties by the surface passivation. From these results, GeOI p–i–n diodes can be promising device candidates for silicon photonics by improving process conditions.

Improving Optical Properties of Ge Layers Fabricated by Epitaxial Growth Combined with Ge Condensation

Katsuya Oda, Kazuki Tani, Shin-ichi Saito, Tadashi Okumura, and Tatemi Ido — 2012-04-20T09:00:00+09:00

Authors: Katsuya Oda, Kazuki Tani, Shin-ichi Saito, Tadashi Okumura, and Tatemi Ido
Single crystal Ge layers were successfully fabricated on the buried oxide layer of a silicon-on-insulator wafer using a combined technique of two-step selective epitaxial growth and Ge condensation. X-ray diffraction measurements revealed that the single crystal Ge layer formed on the buried oxide layer had a tensile strain of 0.07% on the <110> lattice plane in a large unpatterned area. Furthermore, a steep photoluminescence spectrum was obtained from Ge stripes fabricated on the buried oxide layer, and a red shift in the photoluminescence peak was observed due to tensile strain with a wavelength of 1620 nm. The peak intensity of a 10-mm-wide Ge stripe on the buried oxide layer was three times higher than that on a Ge stripe on an Si substrate, which was achieved by improving the crystallinity and carrier confinement within the Ge stripes. These results indicate that this combined technique efficiently improves the performance of Ge light-emitting devices.

Light Output Enhancement of GaN-Based Light-Emitting Diodes by Optimizing SiO_{2} Nanorod-Array Depth Patterned Sapphire Substrate

2012-04-20T09:00:00+09:00

Authors: Ching-Hsueh Chiu, Po-Min Tu, Shih-Pang Chang, Chien-Chung Lin, Chung-Ying Jang, Zhen-Yu Li, Hung-Chih Yang, Hsiao-Wen Zan, Hao-Chung Kuo, Tien-Chang Lu, Shing-Chung Wang, and Chun-Yen Chang
In this study, we investigated high-efficiency InGaN/GaN light-emitting diodes (LEDs) grown on sapphire substrates with SiO_{2} nanorod arrays (NRAs) of different heights. The GaN film showed an improved crystal quality through X-ray diffraction (XRD) full-width at half-maximum (FWHM), photoluminescence (PL), and cathodoluminescence (CL) measurements. The light output power and internal quantum efficiency (IQE) of the fabricated LEDs were increased when compared with those of conventional LEDs. Transmission electron microscopy (TEM) images suggested that the voids between SiO_{2} nanorods and the stacking faults introduced during the nanoscale epitaxial lateral overgrowth (NELOG) of GaN can effectively reduce the threading dislocation density (TDD). We believe that the improvements could be attributed to both the enhanced light extraction by utilizing SiO_{2} NRAs and the improved crystal quality through the NELOG method. We found that the sample with SiO_{2} NRA structures of 200 nm height can increase the LED output power by more than 70% in our study.

Basic Study of Coupling on Three-Dimensional Crossing of Si Photonic Wire Waveguide for Optical Interconnection on Inter or Inner Chip

2012-04-20T09:00:00+09:00

Authors: Katsumi Furuya, Ryohei Takei, Toshihiro Kamei, Youichi Sakakibara, and Masahiko Mori
For speeding up of transmission and energy saving on inter or inner chips of semiconductors, hydrogenated amorphous silicon (a-Si:H), unlike conventional crystal Si (c-Si), promises optical multilevel wiring on a Si IC. For three-dimensional (3D) crossing of Si/a-Si:H photonic wire waveguides, the loss and crosstalk as S-parameters of the two propagation modes are evaluated by numerical analysis at the C-band when the waveguide core is 200 ×400 nm^{2}. Whether the crosstalk can be suppressed to -50 dB or less is to be a criterion. Even at the crossing angle of 30°, when the distance between the waveguides of the crossing is 1 µm or less, the crosstalk is suppressed sufficiently, while the radiation loss is also small if a TE-like mode propagates. These quantitative results are derived for the first time and show that the photonic 3D crossing can rival the present electric multilevel wiring from the viewpoint of device height. An important index for the 3D waveguide crossing fabrication is obtained.

Structural and Luminescence Properties of Highly Crystalline ZnO Nanoparticles Prepared by Sol–Gel Method

2012-04-20T09:00:00+09:00

Authors: Wiem Bousslama, Habib Elhouichet, Bernard Gelloz, Brigitte Sieber, Ahmed Addad, Myriam Moreau, Mokhtar Férid, and Nobuyoshi Koshida
ZnO nanoparticles were synthesized using sol–gel method. The structural and optical properties were investigated by X-ray diffraction (XRD), scanning electron microscopy (SEM), transmission electron microscopy (TEM), high resolution TEM (HRTEM), Raman spectroscopy, and photoluminescence (PL). XRD analysis demonstrates that the nanoparticles have the hexagonal wurtzite structure and the particle size is increased with annealing temperature. The average size of the nanoparticles was determined by SEM as well as XRD data and found to be ∼50 nm after annealing at 800 °C. A sharp, strong and dominant UV emission with a suppressed green emission has been observed at 300 and 10 K, indicating the good optical properties of ZnO nanoparticles. The 10 K UV band is dominated by a neutral-donor bound exciton, and the surface-related SX emission at 3.31 eV is evidenced.

Experimental Analysis of Optical Fiber Multimode Interference Structure and its Application to Refractive Index Measurement

Shuji Taue, Yoshiki Matsumoto, Hideki Fukano, and Kenji Tsuruta — 2012-04-20T09:00:00+09:00

Authors: Shuji Taue, Yoshiki Matsumoto, Hideki Fukano, and Kenji Tsuruta
We investigated a fiber-based multimode interference phenomenon in the wavelength domain by using a white light source and an optical spectrum analyzer. This phenomenon was produced by a larger-core optical fiber joined at both ends with smaller-core optical fibers. We examined the variation of interference wavelength with changes in the length of the larger-core fiber. The interference wavelengths were blue-shifted and the interference signals were sharpened with an increase in the length of the larger-core fiber. The calculated results agreed well with the measured results. Next, we investigated how the input and output fibers with a small core influence the interference signal characteristics. By comparing the amplitude differences of the interference signal we find the conditions of input and output (I/O) fibers for higher sensitivity. In addition, an interference-signal shift was observed by changing the medium surrounding an multimode interference (MMI) structure. The amount of shift increased at a longer wavelength. This leads to the sensitive detection of the refractive index. Finally, a demonstration of the optical fiber refractometer with a multimode interference structure was given by refractive-index measurements of ethanol/water solutions.

GaN-Based Metal–Insulator–Semiconductor Ultraviolet Photodetectors with CsF Current-Suppressing Layer

2012-04-20T09:00:00+09:00

Authors: Chin-Hsiang Chen, Chia-Ming Tsai, Chung-Fu Cheng, Shuo-Fu Yen, Peng-Yin Su, Yu-Hsuan Tsai, and Cheng-Nan Tsai
GaN metal–insulator–semiconductor (MIS) ultraviolet (UV) photodetectors (PDs) with the CsF current-suppressing layer were, for the first time, fabricated and characterized successfully. It was found that we can achieve a low dark current and large photocurrent-to-dark-current contrast ratio from the proposed devices with the use of the CsF current-suppressing layer. With a 5 V applied bias, it was found that the leakage current of the fabricated MIS PDs with the CsF current-suppressing layer was 7.1×10^{-10} A. This small leakage current should be attributed to the large barrier height caused by the insertion of the CsF current-suppressing layer. With a 5 V applied bias, the barrier height of Φ_{B} = 0.942 can be calculated from the dark current–voltage (I–V) characteristics. We can also achieve a large UV-to-visible rejection ratio from the PDs with the CsF current-suppressing layer.

Tilted Domain and Indium Content of InGaN Layer on m-Plane GaN Substrate Grown by Metalorganic Vapor Phase Epitaxy

2012-04-20T09:00:00+09:00

Authors: Kanako Shojiki, Takashi Hanada, Takaaki Shimada, Yuhuai Liu, Ryuji Katayama, and Takashi Matsuoka
The accurate alloy composition of a nonpolar InGaN grown on m-plane GaN is estimated from X-ray reciprocal-space maps (RSMs) of (20-21) and (21-30) diffractions. In this estimation, the anisotropic residual strain in m-plane is carefully considered. In order to avoide the error which may be generated by the anisotropic strain and tilted domains in the film of InGaN, the lattice constants along m-, a-, and c-directions are determined using a pair of two RSMs normalized to the unit reciprocal vector along m-direction. The indium content of InGaN is derived from RSMs data using Poisson effect and Vegard's law. Based on this method, the incorporation of indium into InGaN is investigated. This incorporation is found to be promoted with the increase in the substrate miscut angle and the growth rate. From the precise analysis of RSMs, some of the InGaN domains on m-plane GaN substrates are found to be tilted toward ±a-direction despite of the substrate miscut toward c-direction.

Effect of Phase Purity on Dislocation Density of Pressurized-Reactor Metalorganic Vapor Phase Epitaxy Grown InN

2012-04-20T09:00:00+09:00

Authors: Takuya Iwabuchi, Yuhuai Liu, Takeshi Kimura, Yuantao Zhang, Kiattiwut Prasertsuk, Haruna Watanabe, Noritaka Usami, Ryuji Katayama, and Takashi Matsuoka
The effect of the metastable zincblende (ZB) InN inclusion in the stable wurtzite (WZ) InN on the threading dislocation densities (TDDs) of an InN film grown by pressurized-reactor metalorganic vapor phase epitaxy has been studied by X-ray diffraction measurements. InN films are directly grown on c-plane sapphire substrates with nitrided surfaces at 1600 Torr with the different growth temperature from 500 to 700 °C. Films including ZB-InN show the correlation between the ZB volume fraction and the edge component of TDDs, not the screw component of TDDs. This result can be crystallographically understood by a simple model explaining how the ZB structure is included, i.e., ZB domains existing side-by-side with WZ domains and twined ZB domains. This can be clearly observed by electron backscatter diffraction.

In-Plane Grain Orientation Alignment of Polycrystalline Silicon Films by Normal and Oblique-Angle Ion Implantations

Anri Nakajima, Shin-Ichiro Kuroki, Shuntaro Fujii, and Takashi Ito — 2012-04-20T09:00:00+09:00

Authors: Anri Nakajima, Shin-Ichiro Kuroki, Shuntaro Fujii, and Takashi Ito
Random crystallographic orientations of polycrystalline silicon (poly-Si) grains in the films grown on a SiO_{2} substrate by chemical vapor deposition were laterally aligned by maintaining the 110 restricted pillar texture through double Si^{+} self-ion implantations. The in-plane X-ray diffraction pattern and rocking curve clearly indicate the lateral alignment. The oblique-angle Si^{+} self-ion implantation was also found to be useful for increasing the amount of the 110 pillar texture. The electron backscatter diffraction (EBSD) pattern supports the increase in the amount of the 110 pillar texture and the lateral crystal orientation alignment. The transmission electron micrography and EBSD results also suggest that grain size is increased by double Si^{+} self-ion implantations. Although further systematic optimization may be required, the technique will be useful for improving the electrical characteristics of poly-Si devices for future electronic systems on insulators.

Tuning Optical Properties of Two-Dimensional Ordered Arrays of Silica/Gold and Silver Core/Shell Structured Nanoparticles in Near-Infrared Region

Kosuke Sugawa, Tatsuya Sakai, Daido Tanaka, and Tsuyoshi Akiyama — 2012-04-20T09:00:00+09:00

Authors: Kosuke Sugawa, Tatsuya Sakai, Daido Tanaka, and Tsuyoshi Akiyama
Core/shell type nanoparticles, in which the shell consists of a thin layer of metal and the core consists of monodispersed dielectric nanoparticles, are of great interest owing to their characteristic plasmonic properties. In this study, we have fabricated highly regular two-dimensional arrays of silica-core/gold (or silver)-shell nanoparticles protected with polyvinylpyrrolidone (PVP) by drop-casting their colloidal ethanol solutions onto tilted glass plates. The structure and plasmonic properties of the arrays were evaluated by visible/near-infrared transmission absorption spectroscopy and scanning electron microscopy (SEM). The characteristic broad plasmon band in the near-infrared wavelength region, derived from a hybridized mode of dipolar plasmon modes of the individual core/shell nanoparticle, appeared by changing the concentration of PVP added.

Strain Effects on Avalanche Multiplication in a Silicon Nanodot Array

Nobuya Mori, Hideki Minari, Shigeyasu Uno, Hiroshi Mizuta, and Nobuyoshi Koshida — 2012-04-20T09:00:00+09:00

Authors: Nobuya Mori, Hideki Minari, Shigeyasu Uno, Hiroshi Mizuta, and Nobuyoshi Koshida
Strain effects on avalanche multiplication in a one-dimensional Si nanodot array have been theoretically studied. Compressive strain has two competing effects of the band-gap narrowing and the level-separation widening. The former reduces the ionization threshold and the latter reduces the impact ionization rate for higher energy region. Larger carrier multiplication factor is observed under compressive strain condition.

Bidirectional Two-Terminal Switching Device for Non-Volatile Random Access Memory

Gyu-Hyun Kil, Hyung-Jun Yang, Gae-Hun Lee, Seong-Hyun Lee, and Yun-Heub Song — 2012-04-20T09:00:00+09:00

Authors: Gyu-Hyun Kil, Hyung-Jun Yang, Gae-Hun Lee, Seong-Hyun Lee, and Yun-Heub Song
A two-terminal N^{+}/P/N^{+} Si junction device that can replace the conventional selective transistor was studied as a bilateral switching device for spin transfer torque magnetic random access memory (STT-MRAM), by three-dimensional device simulation. An N^{+}/P/N^{+} junction structure with 30×30 nm^{2} area provides sufficient bidirectional current flow to write data by a drain-induced barrier lowering (DIBL) under a reverse bias at the N^{+}/P (or P/N^{+}) junction, and high current on/off ratio of 10^{6}, which is acceptable for STT-MRAM. In this work, critical parameters such as P-length, P doping, and N^{+} doping are investigated to elucidate the optimal parameter condition in view of write current and current on/off ratio.

Room-Temperature Fabrication of HfON Gate Insulator for Low-Voltage-Operating Pentacene-Based Organic Field-Effect Transistors

Min Liao, Hiroshi Ishiwara, and Shun-ichiro Ohmi — 2012-04-20T09:00:00+09:00

Authors: Min Liao, Hiroshi Ishiwara, and Shun-ichiro Ohmi
Low-voltage-operating pentacene-based organic field-effect transistors (OFETs) with different channel lengths have been fabricated by employing a room-temperature-processed HfON gate insulator. It was found that the on/off current ratio of the OFETs can be improved by decreasing the channel length. However, the hole mobility in the OFETs decreases with decreasing channel length owing to the effect of contact resistance. Interestingly, such OFETs with a short channel length (channel W/L = 500/50 µm) also show good electrical properties, such as a high hole mobility of 0.26 cm^{2} V^{-1} s^{-1}, a low subthreshold swing of 0.13 V/decade, and a large on/off current ratio of 1×10^{5} at an operating voltage of -2 V.

Finite-Difference Time-Domain Analysis of Twist-Defect-Mode Lasing Dynamics in Cholesteric Photonic Liquid Crystal

Tatsunosuke Matsui and Masahiro Kitaguchi — 2012-04-20T09:00:00+09:00

Authors: Tatsunosuke Matsui and Masahiro Kitaguchi
We have numerically investigated lasing dynamics from a twist defect in a cholesteric liquid crystal (CLC) by an auxiliary differential equation finite-difference time-domain (ADE-FDTD) method. As ADEs, the equation of motion of polarization described on the basis of the classical electron oscillator (Lorenz) model and the rate equation in a four-level energy structure are incorporated. A lower lasing threshold has been obtained from the twist-defect mode (TDM) than from band-edge lasing. Standing-wave-like electric fields are strongly localized only in the vicinity where a twist defect is introduced into a CLC, which works as a distributed feedback TDM laser source. The oscillation direction of a standing-wave electric field is not parallel or perpendicular to LC molecules, which is quite different from the bulk CLC case. Our results may be useful for creating more efficient TDM-based CLC lasers.

6,13-Bis(triisopropylsilylethynyl) Pentacene Organic Field-Effect Transistors Utilizing Poly(p-silsesquioxane) Insulating Layers with Various Ratios of Phenol Groups

Yuta Nakanishi, Hirotake Kajii, Koki Tamura, and Yutaka Ohmori — 2012-04-20T09:00:00+09:00

Authors: Yuta Nakanishi, Hirotake Kajii, Koki Tamura, and Yutaka Ohmori
The effects of the hydroxyl group of polymer gate insulators on the characteristics of p-type 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene)-based organic field-effect transistors (OFETs) using poly(p-silsesquioxane) (PSQ) derivatives, which contained various ratios of a phenol group with a hydroxyl group bonded to a phenyl ring in the side chain of their molecular structures, were investigated. The hole mobilities of all top-contact bottom-gate-type OFETs with various PSQ insulators were estimated to be on the order of 0.1 cm^{2} V^{-1} s^{-1}. The current on/off ratio of an OFET increased with decreasing ratio of the hydroxyl group. The bottom-contact devices with photocrosslinked PSQ insulators containing a low ratio of the phenol group exhibited p-channel FET characteristics with a high field-effect mobility of 0.1 cm^{2} V^{-1} s^{-1} and negligible hysteresis in both output and transfer characteristics. An OFET driven at an operating voltage of 10 V was achieved by using the thin 120-nm-thick photocrosslinked PSQ insulator.

Analysis of the Performance of an Inverter Circuit: Varying the Thickness of the Active Layer in Polymer Thin Film Transistors with Circuit Simulation

Luis Reséndiz, Magali Estrada, Antonio Cerdeira, and Víctor Cabrera — 2012-04-20T09:00:00+09:00

Authors: Luis Reséndiz, Magali Estrada, Antonio Cerdeira, and Víctor Cabrera
In this paper, we study, through simulation, the effects on the behavior of an inverter circuit when the active layer thickness of the polymer thin film transistor design is modified. A previously developed compact model for polymer transistors was implemented in standardized hardware description language. We validate results with measured characteristics of transistors fabricated with a poly(methyl methacrylate) layer on top of a poly(3-hexylthiophene-2,5-diyl). This analysis indicates that decreasing the thickness of the active layer can increase the output voltage swing and hence the noise margin in digital circuits. Higher noise margin and larger gain were found for inverters with active layer thicknesses less than 40 nm.

Structural and Ferroelectric Characterization of Uniaxially Oriented Vinylidene Fluoride Oligomer Thin Films

2012-04-20T09:00:00+09:00

Authors: Yusuke Kuroda, Yasuko Koshiba, Masahiro Misaki, Satoshi Horie, Kenji Ishida, and Yasukiyo Ueda
A uniaxially oriented film of ferroelectric vinylidene fluoride (VDF) oligomer was fabricated by vacuum deposition on a friction-transferred vinylidene fluoride–trifluoroethylene copolymer; i.e., P(VDF/TrFE), film as a structural template. Fourier transform infrared spectroscopy and scanning electron microscopy measurements revealed that the ultra thin P(VDF/TrFE) film induced the formation of the ferroelectric form I crystal phase and the uniaxial orientation of what to the VDF oligomer by epitaxial growth. The VDF oligomer/P(VDF/TrFE) films exhibit ferroelectric hysteresis loops with a coercive field and a remanent polarization of 150 MV/m and 77 mC/m^{2}, respectively; however, VDF oligomer films without a structural template showed no ferroelectric properties.

Enhancing the Performance of Pentacene-Based Organic Thin Film Transistors by Inserting Stacked N,N '-Diphenyl-N,N '-bis(1-naphthyl-phenyl)-(1,1'-biphenyl)-4,4'-diamine and Tris(8-hydroxyquinolino)-aluminum Buffer Layers

2012-04-20T09:00:00+09:00

Authors: Chung-Ming Wu, Shui-Hsiang Su, Wei-Chih Weng, Hsiang-Lin Tsai, and Meiso Yokoyama
Organic thin-film transistors (OTFTs) were fabricated using various buffer layers between the active layer and source/drain electrodes. The device structure was glass/indium–tin oxide (ITO)/poly(methyl methacrylate) (PMMA)/pentacene/buffer layer/Ag (source/drain). N,N '-diphenyl-N,N '-bis(1-naphthyl-phenyl)-(1,1'-biphenyl)-4,4'-diamine (NPB), tris(8-hydroxyquinolino)-aluminum (Alq_{3}), Alq_{3}/NPB, and NPB/Alq_{3} films were used as the buffer layers, respectively. The OTFTs using stacked NPB/Alq_{3} as a buffer layer exhibited a field-effect mobility of 0.31 cm^{2} V^{-1} s^{-1}, on–off drain current ratio of 6.7×10^{5}, and threshold voltage of -16.8 V. Additionally, the interface mechanism and contact resistance were determined by ultraviolet photoelectron spectroscopy (UPS) and the transmission line method (TLM). Experimental results indicate that a low energy barrier between the electrode and pentacene enhances the ability of holes to transfer from an electrode to pentacene. Moreover, inserting a buffer layer between the electrode and pentacene reduces the contact resistance. Such an improvement is attributed to the weak interface dipole at the interface of the active layer and electrodes.

Light-Emitting Field-Effect Transistors Having Metal Electrodes Modified with an Organic Thin Film

Akinori Okada, Yoshihide Fukaya, Shu Hotta, and Takeshi Yamao — 2012-04-20T09:00:00+09:00

Authors: Akinori Okada, Yoshihide Fukaya, Shu Hotta, and Takeshi Yamao
We have improved the emission properties and the carrier mobilities of organic light-emitting field-effect transistors (OLEFETs) by modifying the metal electrode(s) with a thin film of n-type thiophene/phenylene co-oligomer (TPCO). Their semiconductor layer was a p-type TPCO crystal. When we used the modified electrode for electron injection, the device exhibited eight times higher emission intensity than a device with unmodified electrodes. By contrast, employing the modified electrode as the hole injection contact, we achieved the maximum hole mobility of 0.11 cm^{2}·V^{-1}·s^{-1} under the hole-enhancement mode. The modified electrodes effectively functioned for injecting both electrons and holes into the p-type crystal. The origin of this is briefly discussed.

Structural and Molecular Changes of C_{60} Thin Films with Incorporated Magnesium Atoms

Crisóforo Morales, Nobuaki Kojima, Seiji Nishi, and Masafumi Yamaguchi — 2012-04-20T09:00:00+09:00

Authors: Crisóforo Morales, Nobuaki Kojima, Seiji Nishi, and Masafumi Yamaguchi
Crystalline changes determined from the diffraction patterns of X-rays in C_{60} films were observed when magnesium atoms were incorporated into C_{60} films grown on mica substrates. The low full width at half maximum (FWHM) value for Mg-doped C_{60} on the mica substrate indicates the high crystalline quality at low magnesium concentrations. Infrared modes that were initially inactive became active owing to the interaction of magnesium atoms with the C_{60} molecule cage. The presence of the lines of triangular cyclic trimers suggests the presence of partially decomposed rhombohedral and rhombohedral polymers. Intermolecular bonds formed owing to the formation of polymeric phases in the film are responsible for the crystalline quality deterioration.

Fundamental Study on Organic Solar Cells Based on Soluble Zinc Phthalocyanine

Ichiko Yamada, Masashi Umeda, Yasuhiko Hayashi, Tetsuo Soga, and Norio Shibata — 2012-04-20T09:00:00+09:00

Authors: Ichiko Yamada, Masashi Umeda, Yasuhiko Hayashi, Tetsuo Soga, and Norio Shibata
We investigated the potential of trifluoroethoxy-coated phthalocyanine [(4TFEO)_{4}-ZnPc] as an organic thin-film solar cell material. (4TFEO)_{4}-ZnPc dissolves well in several organic solvents, thus a fluorinated phthalocyanine (Pc) thin film can be fabricated by a wet process. Additionally, (4TFEO)_{4}-ZnPc has lowest unoccupied molecular orbital (LUMO) energy level close to that of a fullerene derivative owing to the electron-withdrawing effect of fluorine substituents. We fabricated two types of fluorinated Pc solar cells by spin casting “(4TFEO)_{4}-ZnPc single-layer solar cells” and “two-layer heterojunction solar cells” consisting of a (4TFEO)_{4}-ZnPc layer and a poly(3-hexylthiophene) (P3HT) layer. P3HT is a common donor solar cell material. On the other hand, we used (4TFEO)_{4}-ZnPc as an acceptor material. For the single-layer solar cells, the (4TFEO)_{4}-ZnPc film acts as the photoactive layer of the solar cells, and P3HT/(4TFEO)_{4}-ZnPc solar cell properties were improved as compared with that of P3HT or (4TFEO)_{4}-ZnPc single-layer solar cells. Additionally, the photovoltaic properties of these solar cells were significantly improved by annealing treatment.

Organic Solar Cells Based on Electrodeposited Polyaniline Films

Kei Inoue, Tsuyoshi Akiyama, Atsushi Suzuki, and Takeo Oku — 2012-04-20T09:00:00+09:00

Authors: Kei Inoue, Tsuyoshi Akiyama, Atsushi Suzuki, and Takeo Oku
Polyaniline thin films as hole transporting layers were fabricated on transparent indium–tin-oxide electrodes by electrodeposition of aniline in an aqueous H_{2}SO_{4} electrolyte solution. Emerald-green polyaniline films were obtained, which showed stable redox waves. A mixed solution of polythiophene and fullerene derivative was spin-coated onto the electrodeposited polyaniline film. After the modification of titanium oxide film on the surface of the polythiophene/fullerene layer, an aluminum electrode was fabricated by vacuum deposition. The obtained solar cells generated stable photocurrent and photovoltage under light illumination.

Silicon Based System for Single-Nucleotide-Polymorphism Detection: Chip Fabrication and Thermal Characterization of Polymerase Chain Reaction Microchamber

2012-04-20T09:00:00+09:00

Authors: Bivragh Majeed, Ben Jones, Deniz S. Tezcan, Nina Tutunjyan, Luc Haspeslagh, Sara Peeters, Paolo Fiorini, Maaike Op de Beeck, Chris Van Hoof, Maki Hiraoka, Hiroyuki Tanaka, and Ichiro Yamashita
A single nucleotide polymorphism (SNP) is a difference in the DNA sequence of one nucleotide only. We recently proposed a lab-on-a-chip (LoC) system which has the potentiality of fast, sensitive and highly specific SNP detection. Most of the chip components are silicon based and fabricated within a single process. In this paper, the newly developed fabrication method for the silicon chip is presented. The robust and reliable process allows etching structures on the same chip with very different aspect ratios. The characterization of a crucial component to the LoC SNP detector, the microreactor where DNA amplification is performed, is also detailed. Thanks to innovative design and fabrication methodologies, the microreactor has an excellent thermal isolation from the surrounding silicon substrate. This allows for highly localized temperature control. Furthermore, the microreactor is demonstrated to have rapid heating and cooling rates, allowing for rapid amplification of the target DNA fragments. Successful DNA amplification in the microreactor is demonstrated.

Sub-micro-liter Electrochemical Single-Nucleotide-Polymorphism Detector for Lab-on-a-Chip System

2012-04-20T09:00:00+09:00

Authors: Hiroyuki Tanaka, Paolo Fiorini, Sara Peeters, Bivragh Majeed, Tom Sterken, Maaike Op de Beeck, Miho Hayashi, Hidenobu Yaku, and Ichiro Yamashita
A sub-micro-liter single-nucleotide-polymorphism (SNP) detector for lab-on-a-chip applications is developed. This detector enables a fast, sensitive, and selective SNP detection directly from human blood. The detector is fabricated on a Si substrate by a standard complementary metal oxide semiconductor/micro electro mechanical systems (CMOS/MEMS) process and Polydimethylsiloxane (PDMS) molding. Stable and reproducible measurements are obtained by implementing an on-chip Ag/AgCl electrode and encapsulating the detector. The detector senses the presence of SNPs by measuring the concentration of pyrophosphoric acid generated during selective DNA amplification. A 0.5-µL-volume detector enabled the successful performance of the typing of a SNP within the ABO gene using human blood. The measured sensitivity is 566 pA/µM.

Analysis of Sharp Dip Structures on Terahertz Transmission Spectra of Metallic Meshes

Takayuki Hasebe, Yuki Yamada, and Hitoshi Tabata — 2012-04-20T09:00:00+09:00

Authors: Takayuki Hasebe, Yuki Yamada, and Hitoshi Tabata
Metallic meshes are designed for anomalous transmission phenomena in the THz region, which originates from the two contributions: one involves the surface waves excitations generated through periodically arranged metal holes, the other involves the half-wavelength resonance of the metal hole. Furthermore, metallic meshes are used to observe the sharp dip in the transmission spectrum. The sharp dip structure is very sensitive to change in the refractive index of materials attached on metallic meshes. However, the origin of the dip structure is still unclear. In this work, we investigate optical response of the dip structure in the THz region from experimental and theoretical viewpoints. It is found that the dip structure is related to cutoff frequency in the electric field distribution based on a transverse electric 11 (TE_{11}) mode of the rectangular waveguide. Finally, we suggest a theoretical equation in order to explain the dip structure.

Anisotropic Weak Anti-Localization under In-Plane Magnetic Field and Control of Dimensionality via Spin Precession Length

Shun Nonaka, Yoji Kunihashi, Makoto Kohda, and Junsaku Nitta — 2012-04-20T09:00:00+09:00

Authors: Shun Nonaka, Yoji Kunihashi, Makoto Kohda, and Junsaku Nitta
We have examined the newly proposed method in order to electrically deduce the ratio between the Rashba and Dresselhaus spin–orbit interaction (SOI) parameters. Anisotropic magneto-conductance in gate-fitted InGaAs narrow wires is observed under an in-plane magnetic field. From the comparison between experiments and calculated Rashba SOI parameters, we have found that the method is applicable only when the wire width is shorter than the spin precession length. A transition from narrow wires to two-dimensional (2D) wires is observed both by decreasing the spin precession length and by increasing wire width.

Design of a Compact Nonvolatile Four-Input Logic Element Using a Magnetic Tunnel Junction and Metal–Oxide–Semiconductor Hybrid Structure

Daisuke Suzuki, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu — 2012-04-20T09:00:00+09:00

Authors: Daisuke Suzuki, Masanori Natsui, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu
A nonvolatile logic element (NV-LE) using a magnetic tunnel junction (MTJ) and metal–oxide–semiconductor (MOS)-hybrid structure is proposed for a high-density field-programmable gate array with an instant-on capability. Since the output current level of a multiplexer tree including MTJ devices is directly evaluated and amplified by a single differential amplifier on the final stage of the LUT circuit, the number of wasted sense amplifiers is greatly reduced and a compact 4-input NV-LE can be implemented. Moreover, the use of dynamic current-mode logic based circuitry makes it possible a high-speed operation with low-active power dissipation due to the elimination of steady current-path. In fact, the proposed 4-input NV-LE reduces transistor counts to 63% with no performance degradation compared to those of a conventional complementary-MOS-based implementation.

Physics-Based SPICE Model of Spin-Torque Oscillators

Hyein Lim, Sora Ahn, Seungjun Lee, and Hyungsoon Shin — 2012-04-20T09:00:00+09:00

Authors: Hyein Lim, Sora Ahn, Seungjun Lee, and Hyungsoon Shin
The spin-torque oscillator (STO) is a new compact device operating as a tunable RF oscillator in the tens of gigahertz range whose characteristics are determined by the applied current and magnetic field. In this paper, we present a physics-based empirical circuit-level model of an STO that is compatible with circuit-level simulators such as SPICE. The characteristics of an STO are modeled as physics-based analytic functions of the applied current and external magnetic field. The validity of our model was verified by the HSPICE simulation of a current mirror circuit that contains an STO element. The simulation results are in good agreement with the experimental data in the normal operation range. High-order nonlinear effects at large currents are not included in our model because there is no theoretical equation available yet that can precisely explain these effects.

Relative Vortex State Control in a Co/Cu/Co Pseudo-Spin-Valve Ring

2012-04-20T09:00:00+09:00

Authors: Ahmet S. Demiray, Tetsuya Miyawaki, Yusuke Watanabe, Makoto Kohda, Kesami Saito, Seiji Mitani, Koki Takanashi, and Junsaku Nitta
The magnetization reversal process of a Co/Cu/Co pseudo-spin-valve ring structure has been investigated by magneto-resistance measurements and micromagnetic simulations. Major-loop measurement reveals four distinct magnetic configurations between the top and bottom Co rings. We conducted minor-loop measurements with a fixed vortex configuration in the bottom Co ring while the magnetic state of the top Co ring was changed between the onion and vortex states. It was found that the parallel vortex between the top and bottom rings shows a stable magnetization state when the top Co ring is not fully saturated in the onion state, in which the local vortex remains at the ring edge. Micromagnetic simulations also confirm that the local vortex remaining in the top ring contributes to the control of the magnetic parallel vortex state.

Temperature Dependence of Spin Relaxation Time in InAs Columnar Quantum Dots at 10 to 150 K

2012-04-20T09:00:00+09:00

Authors: Sota Nakanishi, Kazutoshi Sasayama, Yoshitsugu Oyanagi, Ryo Yamaguchi, Shulong Lu, Lianhe Li, Andrea Fiore, and Atsushi Tackeuchi
We have investigated carrier spin relaxation in InAs columnar quantum dots (CQDs) using time-resolved photoluminescence measurement. The CQDs were formed by depositing a 1.8 monolayer InAs seed dot layer and a short-period GaAs/InAs superlattice (SL). The spin relaxations of the 3- and 35-period SL CQDs show double exponential decay up to 50 and 130 K, respectively. The spin relaxation times of the fast component, whose amplitudes are 4–11 times larger than that of the slow component, are around 100 ps for the two samples. For the 3-period SL CQDs, the fast spin relaxation time shows no temperature dependence up to around 50 K, indicating the relevance of the Bir-Aronov-Pikus process. The slow spin relaxation time of the 35-period SL CQDs was found to decrease from 3.42 ns at 10 K to 0.849 ns at 130 K. This large change may be explained by the Elliott–Yafet process considering acoustic phonon scattering.

Diameter Dependence of Sub-Terahertz AC Response of Metallic Carbon Nanotubes with a Single Atomic Vacancy

Daisuke Hirai, Takahiro Yamamoto, and Satoshi Watanabe — 2012-04-20T09:00:00+09:00

Authors: Daisuke Hirai, Takahiro Yamamoto, and Satoshi Watanabe
The sub-THz AC response of metallic single-walled carbon nanotubes (M-SWNTs) with a single atomic vacancy is investigated theoretically focusing on its diameter dependence. We find that the AC response behaves more capacitively in large-diameter M-SWNTs with a vacancy at the center of the SWNT in contrast to the diameter-independent AC response of a pristine M-SWNT showing the inductive response. This can be understood from the fact that the large-diameter M-SWNTs with a vacancy have more scattering states for electrons around the vacancy than the small-diameter ones. In addition, the threshold of vacancy position from the center of the SWNT, beyond which the inductive response appears regardless of the Fermi level position, is higher for large-diameter M-SWNTs than for small-diameter ones. Moreover, we find that the AC response depends strongly on tube diameter, but not on the type of tube, i.e., armchair or zigzag.

Growth of Horizontally-Aligned Single-Walled Carbon Nanotubes on Sapphire Surface by Needle-Scratching Method

Hiroki Ago, Yasumichi Kayo, and Masaharu Tsuji — 2012-04-20T09:00:00+09:00

Authors: Hiroki Ago, Yasumichi Kayo, and Masaharu Tsuji
We report the growth of single-walled carbon nanotubes (SWNTs) over metal nanoparticles which are formed by scratching sapphire surface with metal wires. The chemical vapor deposition over sapphire substrate scratched with Fe and Co metal wires gives horizontally aligned SWNTs, while no nanotube growth is observed for Au, Mo, and Ni wires. This result suggests that the nanoparticles scattered from Fe and Co wires act as the catalyst for SWNT growth, being different from the previously proposed substrate-catalyzed reaction mechanism. Further, we study the effects of the flow rates of CH_{4}–H_{2} gases during the SWNT growth on the nanotube density and diameter.

Direct Growth Properties of Graphene Layers on Sapphire Substrate by Alcohol-Chemical Vapor Deposition

Atsushi Nakamura, Yuta Miyasaka, and Jiro Temmyo — 2012-04-20T09:00:00+09:00

Authors: Atsushi Nakamura, Yuta Miyasaka, and Jiro Temmyo
Few nanometers thick graphene layers were directly grown on a-plane (11-20) sapphire substrates by alcohol-chemical vapor deposition (alcohol-CVD) using ethanol as a carbon source and without any catalytic metal on the substrate surface. The growth relationship between the graphene layer and substrate was analyzed using a transmission electron microscope (TEM). The growth rate of graphene layers with different growth temperatures revealed that the Al atom act as a catalyst for synthesizing a graphitic material during the decomposition of ethanol. An optical transmittance and a sheet resistance of the graphene sheet directly grown on sapphire substrate were observed. SiO_{2}/Si and n-6H-SiC substrates were also examined for graphene direct growth to discuss the catalytic behavior of Si atoms compared with Al atoms.

Plasma Treatment to Improve Chemical Vapor Deposition-Grown Graphene to Metal Electrode Contact

Taesoo Kwon, Hyosub An, Young-Soo Seo, and Jongwan Jung — 2012-04-20T09:00:00+09:00

Authors: Taesoo Kwon, Hyosub An, Young-Soo Seo, and Jongwan Jung
We show that contact properties of chemical vapor deposition (CVD)-grown graphene to metal electrode can be improved with Ar plasma treatment before metal electrode deposition. The Ar plasma treatment reduced the baseline signal of the Raman spectrum of graphene without changing main peaks of 2D and G peak and increasing D peak, supporting its effectiveness to reduce the polymer residue. Transfer length method (TLM) patterns for the plasma-treated samples exhibit more linear and neat current–voltage curve, and lower contact resistance compared with the control one (no plasma treated sample). These results support that plasma treatment is effective to improve the graphene–metal contact properties by reducing interface polymer residue.

Analysis of Operation Mechanism of Field Effect Transistor Composed of Network of High-Quality Single Wall Carbon Nanotubes by Scanning Gate Microscopy

2012-04-20T09:00:00+09:00

Authors: Xiaojun Wei, Nobuyuki Aoki, Tatsurou Yahagi, Kenji Maeda, Jonathan P. Bird, Koji Ishibashi, and Yuichi Ochiai
Field effect transistors (FETs) whose channel is composed of a network of high-quality single wall carbon nanotubes (SWNTs) have been studied to investigate the mechanism of the device operation via scanning gate microscopy (SGM) at room temperature. SWNTs synthesized by CoMoCAT^{®} process was used for the formation of the network. Clear SGM responses were observed only at some points but not uniformly in a whole of the channel. The observed responses correspond to positions where two SWNTs are crossing. Back gate voltage dependence of the SGM images and an electrostatic force microscopy image were also studied. One of the possible mechanisms of the SGM response is considered as a modulation of Schottky barrier formed at junctions between metallic and semiconducting SWNTs. Such junctions suggestively play an important role in the FET operation.

Effect of Solid-Phase-Epitaxy Si Layers on Suppression of Sb Diffusion from Sb-Doped n^{+}-BaSi_{2}/p^{+}-Si Tunnel Junction to Undoped BaSi_{2} Overlayers

2012-04-20T09:00:00+09:00

Authors: Weijie Du, Takanobu Saito, Muhammad Ajmal Khan, Kaoru Toko, Noritaka Usami, and Takashi Suemasu
A new method is proposed for the growth of undoped BaSi_{2} overlayers on a Sb-doped n^{+}-BaSi_{2}/p^{+}-Si tunnel junction with reduced Sb diffusion. Samples with the structure of undoped-BaSi_{2}/Si/Sb-doped n^{+}-BaSi_{2}/p^{+}-Si were prepared; the inserted Si layer was grown by solid phase epitaxy and used to prevent Sb diffusion during the growth of undoped BaSi_{2} overlayers. Secondary ion mass spectrometry measurements indicated that Sb diffusion was effectively suppressed when the growth temperature of the undoped BaSi_{2} overlayers was 500 °C and lower. The X-ray diffraction (XRD) rocking curves revealed that the full width at half maximum for the BaSi_{2}(600) intensity increased significantly for BaSi_{2} grown at 440 °C, indicating that the growth temperature should be higher than this temperature.

Extraction Enhanced Lateral Insulated Gate Bipolar Transistor: A Super High Speed Lateral Insulated Gate Bipolar Transistor Superior to Lateral Dobule Difused Metal Oxide Semiconductor Field-Effect Transistor

2012-04-20T09:00:00+09:00

Authors: Youichi Ashida, Shigeki Takahashi, Satoshi Shiraki, Norihito Tokura, and Akio Nakagawa
We have successfully developed novel extraction enhanced lateral insulated gate bipolar transistors (E^{2}LIGBTs) in conventional silicon on insulator (SOI) wafers, which exhibit super-high speed switching of 34 ns turn-off time and a low on-state voltage of 3.7 V at 84 A/cm^{2} simultaneously with a high breakdown voltage of 738 V. This is the first report showing its superior switching speed and on-resistance compared to conventional lateral double diffused metal oxide semiconductor field-effect transistor (LDMOS). The superior performance is achieved by a new anode structure designed with the proposed E^{2} concept, which simultaneously achieves enhanced electron extraction and suppression of hole injection at the anode region without life time control. The E^{2} concept is realized using the anode structure, consisting of a narrow p^{+}-injector and a wide Schottky contact on a lightly doped p-layer over an n-buffer. The switching speed can be controlled by the area ratio of the Schottky area over the injector area.

High Voltage and High Reliability Silicon-on-Insulator Power IC Technologies and Their Application to 750 V 4.5 A Micro-Inverter IC

2012-04-20T09:00:00+09:00

Authors: Satoshi Shiraki, Shigeki Takahashi, Akira Yamada, Masahiro Yamamoto, Koji Senda, Youichi Ashida, Atsuyuki Hiruma, and Norihito Tokura
We have successfully developed the record high blocking voltage of 750 V and the largest current capability of 4.5 A silicon-on-insulator (SOI) micro-inverter IC, which is made possible by the newly developed high voltage reliability technology and high-speed and low-dissipation extraction enhanced lateral insulated gate bipolar transistor (E^{2}LIGBT). It has been found, for the first time, that the stable and reliable high blocking voltage of 760 V is assured by controlling the sheet-resistance of the polycrystalline silicon (poly-Si) layer of the scroll-shaped resistive field plate (SRFP). The high voltage and high reliability SOI power IC technology is expected as the key technology enabling 750 V 4.5 A micro-inverter IC for harsh applications such as automotive electronics.

A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage

2012-04-20T09:00:00+09:00

Authors: Ming-Hung Han, Hung-Bin Chen, Chia-Jung Chang, Jia-Jiun Wu, Wen-Chong Chen, Chi-Chong Tsai, and Chun-Yen Chang
In this work, double reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device combines a new implant technology without using additional mask in standard 0.18 µm technology has been proposed and successfully fabricated. The breakdown voltage (BV) can be improved significantly with simply changing the implanted region length in this implant technology. Firstly, hydrodynamic transport simulations which analyze the high bias condition electric field distributions are examined to predict and explain the increase of breakdown voltage. Then the fabricated devices process flow is demonstrated, the structures are performed, and the breakdown voltages increase with different n-type double diffusion (NDD) photoresistor (PR) size using the change of PR exposure dose are investigated. The measurement results show that maximum NDD PR size achieves BV improvement of 6.3%, and 5% increase of figure of merit (FOM) evaluation. Throughout the whole fabrication process, no additional mask and device area show the potential of cost effective with the proposed technique. Such devices with good off-state breakdown voltage and specific on-resistance are very competitive with similar technologies and show good promising in system on chip (SOC) applications.

Reduction of Power Loss of Zero Current Switching Converter by Optimizing Power Devices

2012-04-20T09:00:00+09:00

Authors: Satoru Machida, Naoto Kikuchi, Tsutomu Segawa, Yuichi Shimo, and Masashi Kobayashi
This paper reports on a reduction of the power loss of the zero current switching (ZCS) converter by the power switching devices, the main and auxiliary switch (Si-IGBT), for the first time. The origin of a “current spike” which was observed during ZCS turn-off was investigated, and it was found that this distinctive phenomenon can be eliminated by shortening the turn-off time of main switch. An improvement of the switching loss reduction rate of a hard switching (HS) can be realized by selecting an optimal turn-off time of the main switch. In addition, the optimal turn-off time varies and has a strong correlation with the turn-off time of the auxiliary switch. It became clear that there is an optimal combination in the characteristics of the switching devices of the ZCS. It was confirmed that the power loss of the ZCS was improved by 17% by this power device optimization.

Surface Recombination of Crystalline Silicon Substrates Passivated by Atomic-Layer-Deposited AlO_{x}

2012-04-20T09:00:00+09:00

Authors: Koji Arafune, Shohei Miki, Ryosuke Matsutani, Junpei Hamano, Haruhiko Yoshida, Tomihisa Tachibana, Hyun Ju Lee, Atsuhi Ogura, Yoshio Ohshita, and Shin-ichi Satoh
AlO_{x} films as passivation layers for p-type crystalline silicon were prepared by atomic layer deposition with ozone as an oxidant, and the effects of the AlO_{x} film thickness and deposition temperature on the maximum recombination velocity (S_{max}) were evaluated. S_{max} is improved by increasing the layer thickness but saturates at a layer thickness of about 30 nm. In the case of samples deposited at room temperature, S_{max} is improved fivefold when the thickness is increased from 20 to 33 nm. S_{max} also improved as the deposition temperature was increased to 300 °C then deteriorated when it was further increased to 350 °C. After postdeposition annealing, we obtained an S_{max} of 8.5 cm/s.

Optimization of Amorphous Si/Crystalline Si Heterojunction Solar Cells by BF_{2} Ion Implantation

Tzong-Han Tsai, Yung-Chun Wu, Shih-Sian Yang, and Chun-Hao Chen — 2012-04-20T09:00:00+09:00

Authors: Tzong-Han Tsai, Yung-Chun Wu, Shih-Sian Yang, and Chun-Hao Chen
In this study we evaluated two approaches to improving the efficiency of amorphous Si/crystalline Si (a-Si/c-Si) heterojunction solar cells by BF_{2} ion implantation. First, emitter layer formation was compared for the cases of B and BF_{2} ion implantation when using the same 7° tilt angle. Second, emitter layer formation was compared between a 7° tilt angle and a 60° tilt angle when using BF_{2} ion implantation. The experimental results reveal that the fluorine in BF_{2} passivates the defects at the a-Si and a-Si/c-Si interface, and ion implantation at a high 60° tilt angle forms a shallow solar cell junction. The emitter layer formed by BF_{2} ion implantation with a 60° tilt angle in an a-Si/c-Si heterojunction solar cell achieves the highest short circuit current density (J_{SC}) of 36.85 mA/cm^{2} with a conversion efficiency (η) of 14.41%.

Investigation of Hot Carrier Degradation in Shallow-Trench-Isolation-Based High-Voltage Laterally Diffused Metal–Oxide–Semiconductor Field-Effect Transistors by a Novel Direct Current Current–Voltage Technique

Yandong He and Ganggang Zhang — 2012-04-20T09:00:00+09:00

Authors: Yandong He and Ganggang Zhang
Shallow trench isolation (STI) based laterally diffused metal–oxide–semiconductor (LDMOS) devices have become popular with its better tradeoff between breakdown voltage and on-resistance and its compatibility with the standard complementary metal–oxide–semiconductor (CMOS) process. A novel direct current current–voltage (DCIV) technique demonstrated with multiple sharp peak signals is proposed to characterize interface state generation in the channel and in the STI drift regions separately. Degradation of STI-based LDMOS transistors in various hot-carrier stress modes is investigated experimentally by proposed technique. A two-dimensional numerical device simulation is performed to obtain insight into the proposed technique and device degradation characteristics under hot-carrier stress conditions. The impact of interface state location on device electrical characteristics is analyzed from measurement and simulation. Our results show that the maximum I_{sub} stress becomes the worst hot-carrier degradation mode in term of the on-resistance degradation, which is attributed to interface state generation under STI drift region.

Current Transport Characteristics of Quasi-Al_{x}Ga_{1-x}N/SiC Heterojunction Bipolar Transistors with Various Band Discontinuities

Takafumi Okuda, Hiroki Miyake, Tsunenobu Kimoto, and Jun Suda — 2012-04-20T09:00:00+09:00

Authors: Takafumi Okuda, Hiroki Miyake, Tsunenobu Kimoto, and Jun Suda
The current transport characteristics of quasi-Al_{x}Ga_{1-x}N/SiC heterojunction bipolar transistors (HBTs) with various band discontinuities were investigated in a low-current range using a Gummel plot. In the low-current range, the base currents of the HBTs were dominated by recombination currents. The collector current characteristics of the HBTs in the low-current range were almost the same in spite of the various band discontinuities, and the ideality factor n was 1.0. The band discontinuities at the heterojunction had no effect on electron injection in the low-current range. This is because the collector currents were dominated by diffusion process in the base region rather than by injection process at the AlGaN/SiC interface.

Recent articles in Jpn. J. Appl. Phys.

Water-Related Hole Traps at Thermally Grown GeO_{2}–Ge Interface

Characteristics of Defect Generation and Breakdown in SiO_{2} for Polycrystalline Silicon Channel Field-Effect Transistor

Experimental and Analytical Characterization of Dual-Gated Germanium Junctionless p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors

Channel Strain Measurement in 32-nm-Node Complementary Metal–Oxide–Semiconductor Field-Effect Transistor by Raman Spectroscopy

Experimental Comparisons between Tetrakis(dimethylamino)titanium Precursor-Based Atomic-Layer-Deposited and Physical-Vapor-Deposited Titanium–Nitride Gate for High-Performance Fin-Type Metal–Oxide–Semiconductor Field-Effect Transistors

Passivation of Ge(100) and (111) Surfaces by Termination of Nonmetal Elements

Estimation of Breakdown Electric-Field Strength While Reflecting Local Structures of SiO_{2} Gate Dielectrics Using First-Principles Molecular Orbital Calculation Technique

Fabrication of Graphene Directly on SiO_{2} without Transfer Processes by Annealing Sputtered Amorphous Carbon

Single-Tube Characterization Methodology for Experimental and Analytical Evaluation of Carbon Nanotube Synthesis

Through Silicon Via Fabrication with Low-κ Dielectric Liner and Its Implications on Parasitic Capacitance and Leakage Current

Room-Temperature Microjoining of LSI Chips on Poly(ethylene naphthalate) Film Using Mechanical Caulking of Au Cone Bump

Potential Characterization of Interconnect Corrosion by Kelvin Probe and Electrostatic Force Microscopies

Oxygen-Induced Barrier Failure in Ti-Based Self-Formed and Ta/TaN Barriers for Cu Interconnects

Mn_{2}O_{3} Slurry Reuse by Circulation Achieving High Constant Removal Rate

Board-Level Solder Joint Reliability of Edge- and Corner-Bonded Lead-Free Chip Scale Package Assemblies Subjected to Thermal Cycling

Postannealing Effects on Strain/Crystal Quality of Lateral Source Relaxed/Strained Layer Heterostructures Fabricated by O^{+} Ion Implantation

Recovery Characteristics of Anomalous Stress-Induced Leakage Current of 5.6 nm Oxide Films

Design of Thin-Body Double-Gated Vertical-Channel Tunneling Field-Effect Transistors for Ultralow-Power Logic Circuits

Advanced 10 nm Width Silicon-on-Insulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-Insulator Realization Technology

Nanowire-Width and Dopant-Species Dependences of Carrier Transport Characteristics of Schottky Barrier Source/Drain Nanowire Field-Effect Transistors

Advantages of Silicon Nanowire Metal–Oxide–Semiconductor Field-Effect Transistors over Planar Ones in Noise Properties

Hole Mobility in Accumulation Mode Metal–Oxide–Semiconductor Field-Effect Transistors

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

64 kbit Ferroelectric-Gate-Transistor-Integrated NAND Flash Memory with 7.5 V Program and Long Data Retention

Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-Side Assisted Erase Scheme Using Minimum Channel Length/Width Standard Complemental Metal–Oxide–Semiconductor Single Transistor Cell

Fabrication of Floating-Gate-Type Fin-Channel Double- and Tri-Gate Flash Memories and Comparative Study of Their Electrical Characteristics

Re-Examination of Performance and Reliability Degradation in Metal–Oxide–Nitride–Oxide–Semiconductor Memory with Ultrathin SiN Charge Trap Layers

Robust Data Retention and Superior Endurance of Silicon–Oxide–Nitride–Oxide–Silicon-Type Nonvolatile Memory with NH_{3}-Plasma-Treated and Pd-Nanocrystal-Embedded Charge Storage Layer

Improvement of Uniformity of Resistive Switching Parameters by Selecting the Electroformation Polarity in IrO_{x}/TaO_{x}/WO_{x}/W Structure

Reset Current Reduction with Excellent Filament Controllability by Using Area Minimized and Field Enhanced Unipolar Resistive Random Access Memory Structure

Complementary Metal Oxide Semiconductor Compatible Hf-Based Resistive Random Access Memory with Ultralow Switching Current/Power

Flexible One Diode–One Resistor Crossbar Resistive-Switching Memory

Excellent Uniformity and Multilevel Operation in Formation-Free Low Power Resistive Switching Memory Using IrO_{x}/AlO_{x}/W Cross-Point

Record Resistance Ratio and Bipolar/Unipolar Resistive Switching Characteristics of Memory Device Using Germanium Oxide Solid Electrolyte

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

Electrical Property of DNA Field-Effect Transistor: Charge Retention Property

Areal and Structural Effects on Oxide-Based Resistive Random Access Memory Cell for Improving Resistive Switching Characteristics

Evaluation of the WO_{x} Film Properties for Resistive Random Access Memory Application

Effect of Oxidation Amount on Gradual Switching Behavior in Reset Transition of Al/TiO_{2}-Based Resistive Switching Memory and Its Mechanism for Multilevel Cell Operation

Formation-Polarity-Dependent Improved Resistive Switching Memory Performance Using IrO_{x}/GdO_{x}/WO_{x}/W Structure

Manipulation of Dispersed Magnetic Beads for On-Chip Immunoassay

Multicore Large-Scale Integration Lifetime Extension by Negative Bias Temperature Instability Recovery-Based Self-Healing

Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal–Oxide–Semiconductor Technology Including Its Distance Dependences

0.1 V 13 GHz Transformer-Based Quadrature Voltage-Controlled Oscillator with a Capacitor Coupling Technique in 90 nm Complementary Metal Oxide Semiconductor

High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme

Postfabrication Independent Inductance and Quality Factor Adjustments of On-Chip Inductors by Above-CMOS Processing for Rapid Prototyping of Radio Frequency System on Chips

An Inverter-Based Wideband Low-Noise Amplifier in 40 nm Complementary Metal Oxide Semiconductor

Wireless Charge Based Capacitance Measurement Circuits with On-Chip Spiral Inductor for Radio Frequency Identification Biosensor

An Integrated Amorphous Silicon Gate Driver Circuit Using Voltage-Controlled Capacitance Modeling for High Definition Television

Fully Parallel Self-Learning Analog Support Vector Machine Employing Compact Gaussian Generation Circuits

A Wide-Range Tunable Level-Keeper Using Vertical Metal–Oxide–Semiconductor Field-Effect Transistors for Current-Reuse Systems

Low-Turn-on-Voltage Heterojunction Bipolar Transistors with a C-Doped InGaAsSb Base Grown by Metalorganic Chemical Vapor Deposition

Schottky Source/Drain InAlN/GaN Metal–Insulator–Semiconductor High-Electron-Mobility Transistor with High Breakdown Voltage and Low On-Resistance

High Integrity SiO_{2} Gate Insulator Formed by Microwave-Excited Plasma Enhanced Chemical Vapor Deposition for AlGaN/GaN Hybrid Metal–Oxide–Semiconductor Heterojunction Field-Effect Transistor on Si Substrate

Deep levels in n-GaN Doped with Carbon Studied by Deep Level and Minority Carrier Transient Spectroscopies

Impact of Data Transmission over 10 Gbps on High-Density and Low-Cost Optoelectronic Module with Polynorbornene Waveguides

Large Area of Ultraviolet GaN-Based Photonic Quasicrystal Laser

Femtosecond Laser-Excited Two-Photon Fluorescence Microscopy of Surface Plasmon Polariton

Analysis of Phase Matching Conditions for Generating Second Harmonic in ZnO Channel Waveguides

Terahertz Radiation from a (113)B GaAs/AlAs Coupled Multilayer Cavity Generated by Ultrashort Laser Pulse Excitation

GaAs/AlAs Multilayer Cavity with Er-Doped InAs Quantum Dots Embedded in Strain-Relaxed InGaAs Barriers for Ultrafast All-Optical Switches

Silicon Ring Optical Modulator with p/n Junctions Arranged along Waveguide for Low-Voltage Operation

Electroluminescence from One-Dimensionally Self-Aligned Si-Based Quantum Dots with High Areal Dot Density

Light Detection and Emission in Germanium-on-Insulator Diodes

Improving Optical Properties of Ge Layers Fabricated by Epitaxial Growth Combined with Ge Condensation

Light Output Enhancement of GaN-Based Light-Emitting Diodes by Optimizing SiO_{2} Nanorod-Array Depth Patterned Sapphire Substrate

Basic Study of Coupling on Three-Dimensional Crossing of Si Photonic Wire Waveguide for Optical Interconnection on Inter or Inner Chip

Structural and Luminescence Properties of Highly Crystalline ZnO Nanoparticles Prepared by Sol–Gel Method

Experimental Analysis of Optical Fiber Multimode Interference Structure and its Application to Refractive Index Measurement

GaN-Based Metal–Insulator–Semiconductor Ultraviolet Photodetectors with CsF Current-Suppressing Layer

Tilted Domain and Indium Content of InGaN Layer on m-Plane GaN Substrate Grown by Metalorganic Vapor Phase Epitaxy

Effect of Phase Purity on Dislocation Density of Pressurized-Reactor Metalorganic Vapor Phase Epitaxy Grown InN

In-Plane Grain Orientation Alignment of Polycrystalline Silicon Films by Normal and Oblique-Angle Ion Implantations

Tuning Optical Properties of Two-Dimensional Ordered Arrays of Silica/Gold and Silver Core/Shell Structured Nanoparticles in Near-Infrared Region

Strain Effects on Avalanche Multiplication in a Silicon Nanodot Array

Bidirectional Two-Terminal Switching Device for Non-Volatile Random Access Memory

Room-Temperature Fabrication of HfON Gate Insulator for Low-Voltage-Operating Pentacene-Based Organic Field-Effect Transistors

Finite-Difference Time-Domain Analysis of Twist-Defect-Mode Lasing Dynamics in Cholesteric Photonic Liquid Crystal

6,13-Bis(triisopropylsilylethynyl) Pentacene Organic Field-Effect Transistors Utilizing Poly(p-silsesquioxane) Insulating Layers with Various Ratios of Phenol Groups